forked from OSchip/llvm-project
[mips] Move expansion of .cpsetup to target streamer.
Summary: There are two functional changes: 1) The directive is not expanded for the ASM->ASM code path. 2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3482 llvm-svn: 207741
This commit is contained in:
Matheus Almeida
parent
88fbbcaa30
commit
d92a3fa212
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@ -2361,58 +2361,8 @@ bool MipsAsmParser::parseDirectiveCPSetup() {
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if (Parser.parseIdentifier(Name))
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reportParseError("expected identifier");
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MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
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unsigned GPReg = getGPR(matchCPURegisterName("gp"));
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// FIXME: The code below this point should be in the TargetStreamers.
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// Only N32 and N64 emit anything for .cpsetup
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// FIXME: We should only emit something for PIC mode too.
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if (!isN32() && !isN64())
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return false;
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MCStreamer &TS = getStreamer();
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MCInst Inst;
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// Either store the old $gp in a register or on the stack
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if (SaveIsReg) {
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// move $save, $gpreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(Save));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
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} else {
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// sd $gpreg, offset($sp)
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Inst.setOpcode(Mips::SD);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
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Inst.addOperand(MCOperand::CreateImm(Save));
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}
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
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Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI, getContext());
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const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
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Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO, getContext());
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// lui $gp, %hi(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::LUi);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateExpr(HiExpr));
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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// addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::ADDiu);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateExpr(LoExpr));
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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// daddu $gp, $gp, $funcreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(FuncReg));
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TS.EmitInstruction(Inst, STI);
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getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, *Sym, SaveIsReg);
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return false;
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}
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@ -149,6 +149,24 @@ void MipsTargetAsmStreamer::emitDirectiveCpload(unsigned RegNo) {
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<< StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
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int RegOrOffset,
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const MCSymbol &Sym,
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bool IsReg) {
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OS << "\t.cpsetup\t$"
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<< StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
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if (IsReg)
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OS << "$"
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<< StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
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else
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OS << RegOrOffset;
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OS << ", ";
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OS << Sym.getName() << "\n";
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}
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// This part is for ELF object output.
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MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
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const MCSubtargetInfo &STI)
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@ -456,3 +474,58 @@ void MipsTargetELFStreamer::emitDirectiveCpload(unsigned RegNo) {
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TmpInst.addOperand(MCOperand::CreateReg(RegNo));
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getStreamer().EmitInstruction(TmpInst, STI);
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}
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void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
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int RegOrOffset,
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const MCSymbol &Sym,
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bool IsReg) {
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// Only N32 and N64 emit anything for .cpsetup iff PIC is set.
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if (!Pic || !(isN32() || isN64()))
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return;
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MCAssembler &MCA = getStreamer().getAssembler();
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MCInst Inst;
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// Either store the old $gp in a register or on the stack
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if (IsReg) {
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// move $save, $gpreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(RegOrOffset));
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
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} else {
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// sd $gpreg, offset($sp)
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Inst.setOpcode(Mips::SD);
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateReg(Mips::SP));
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Inst.addOperand(MCOperand::CreateImm(RegOrOffset));
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}
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getStreamer().EmitInstruction(Inst, STI);
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Inst.clear();
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const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
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Sym.getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
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const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
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Sym.getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
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// lui $gp, %hi(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::LUi);
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateExpr(HiExpr));
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getStreamer().EmitInstruction(Inst, STI);
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Inst.clear();
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// addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::ADDiu);
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateExpr(LoExpr));
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getStreamer().EmitInstruction(Inst, STI);
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Inst.clear();
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// daddu $gp, $gp, $funcreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateReg(Mips::GP));
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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getStreamer().EmitInstruction(Inst, STI);
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}
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@ -50,6 +50,8 @@ public:
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// PIC support
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virtual void emitDirectiveCpload(unsigned RegNo) = 0;
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virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
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const MCSymbol &Sym, bool IsReg) = 0;
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};
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// This part is for ascii assembly output
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@ -89,6 +91,8 @@ public:
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// PIC support
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virtual void emitDirectiveCpload(unsigned RegNo);
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void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
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const MCSymbol &Sym, bool IsReg) override;
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};
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// This part is for ELF object output
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@ -137,6 +141,8 @@ public:
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// PIC support
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virtual void emitDirectiveCpload(unsigned RegNo);
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void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
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const MCSymbol &Sym, bool IsReg) override;
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protected:
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bool isO32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
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@ -1,36 +1,78 @@
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=O32 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N32 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N64 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 -filetype=obj -o - %s | \
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# RUN: llvm-objdump -d -r -arch=mips64 - | \
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# RUN: FileCheck -check-prefix=O32 %s
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# TODO: !PIC -> no output
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \
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# RUN: FileCheck -check-prefix=ASM %s
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 -filetype=obj -o - %s | \
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# RUN: llvm-objdump -d -r -arch=mips64 - | \
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# RUN: FileCheck -check-prefix=NXX -check-prefix=N32 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \
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# RUN: FileCheck -check-prefix=ASM %s
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# RUN: llvm-mc -triple mips64-unknown-unknown %s -filetype=obj -o - | \
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# RUN: llvm-objdump -d -r -arch=mips64 - | \
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# RUN: FileCheck -check-prefix=NXX -check-prefix=N64 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown %s | \
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# RUN: FileCheck -check-prefix=ASM %s
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.text
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.option pic2
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t1:
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.cpsetup $25, 8, __cerror
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# ANY-LABEL: t1:
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# O32-NOT: __cerror
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# FIXME: Direct object emission for N32 is still under development.
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# N32 doesn't allow 3 operations to be specified in the same relocation
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# record like N64 does.
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# NXX: sd $gp, 8($sp)
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# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror)))
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# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror)))
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# NXX: lui $gp, 0
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# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
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# NXX: addiu $gp, $gp, 0
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# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
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# N32: addu $gp, $gp, $25
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# N64: daddu $gp, $gp, $25
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# ASM: .cpsetup $25, 8, __cerror
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t2:
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# ANY-LABEL: t2:
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.cpsetup $25, $2, __cerror
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# O32-NOT: __cerror
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# FIXME: Direct object emission for N32 is still under development.
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# N32 doesn't allow 3 operations to be specified in the same relocation
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# record like N64 does.
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# NXX: move $2, $gp
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# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror)))
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# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror)))
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# NXX: lui $gp, 0
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# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror
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# NXX: addiu $gp, $gp, 0
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# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror
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# N32: addu $gp, $gp, $25
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# N64: daddu $gp, $gp, $25
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# ASM: .cpsetup $25, $2, __cerror
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t3:
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.option pic0
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nop
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.cpsetup $25, 8, __cerror
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nop
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# Testing that .cpsetup expands to nothing in this case
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# by checking that the next instruction after the first
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# nop is also a 'nop'.
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# NXX: nop
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# NXX-NEXT: nop
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# ASM: nop
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# ASM: .cpsetup $25, 8, __cerror
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# ASM: nop
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