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Hexagon: Use absolute addressing mode loads/stores for global+offset 

instead of redefining separate instructions for them.

llvm-svn: 175086
This commit is contained in:
Jyotsna Verma 2013-02-13 21:38:46 +00:00
parent f5d710f0b3
commit d92252469e
8 changed files with 309 additions and 1051 deletions
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3
llvm/lib/Target/Hexagon/Hexagon.h
View File

@ -28,7 +28,8 @@ namespace llvm {
class HexagonTargetMachine;
class raw_ostream;
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM);
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
CodeGenOpt::Level OptLevel);
FunctionPass *createHexagonDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createHexagonFPMoverPass(TargetMachine &TM);
FunctionPass *createHexagonRemoveExtendOps(HexagonTargetMachine &TM);

111
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -15,18 +15,29 @@
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonTargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
static
cl::opt<unsigned>
MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
cl::Hidden, cl::init(2),
cl::desc("Maximum number of uses of a global address such that we still us a"
"constant extended instruction"));
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//
namespace llvm {
void initializeHexagonDAGToDAGISelPass(PassRegistry&);
}
//===--------------------------------------------------------------------===//
/// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
/// instructions for SelectionDAG operations.
@ -40,19 +51,24 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
// Keep a reference to HexagonTargetMachine.
HexagonTargetMachine& TM;
const HexagonInstrInfo *TII;
DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
public:
explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine)
: SelectionDAGISel(targetmachine),
explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(targetmachine, OptLevel),
Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
TM(targetmachine),
TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
}
bool hasNumUsesBelowThresGA(SDNode *N) const;
SDNode *Select(SDNode *N);
// Complex Pattern Selectors.
inline bool foldGlobalAddress(SDValue &N, SDValue &R);
inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
@ -113,10 +129,23 @@ inline SDValue XformU7ToU7M1Imm(signed Imm) {
/// createHexagonISelDag - This pass converts a legalized DAG into a
/// Hexagon-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM) {
return new HexagonDAGToDAGISel(TM);
FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new HexagonDAGToDAGISel(TM, OptLevel);
}
static void initializePassOnce(PassRegistry &Registry) {
const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
PassInfo *PI = new PassInfo(Name, "hexagon-isel",
&SelectionDAGISel::ID, 0, false, false);
Registry.registerPass(*PI, true);
}
void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
CALL_ONCE_INITIALIZATION(initializePassOnce)
}
static bool IsS11_0_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
@ -1526,3 +1555,69 @@ bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
return (UseCount <= 1);
}
//===--------------------------------------------------------------------===//
// Return 'true' if use count of the global address is below threshold.
//===--------------------------------------------------------------------===//
bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
assert(N->getOpcode() == ISD::TargetGlobalAddress &&
"Expecting a target global address");
// Always try to fold the address.
if (TM.getOptLevel() == CodeGenOpt::Aggressive)
return true;
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
GlobalAddressUseCountMap.find(GA->getGlobal());
if (GI == GlobalAddressUseCountMap.end())
return false;
return GI->second <= MaxNumOfUsesForConstExtenders;
}
//===--------------------------------------------------------------------===//
// Return true if the non GP-relative global address can be folded.
//===--------------------------------------------------------------------===//
inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
return foldGlobalAddressImpl(N, R, false);
}
//===--------------------------------------------------------------------===//
// Return true if the GP-relative global address can be folded.
//===--------------------------------------------------------------------===//
inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
return foldGlobalAddressImpl(N, R, true);
}
//===--------------------------------------------------------------------===//
// Fold offset of the global address if number of uses are below threshold.
//===--------------------------------------------------------------------===//
bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
bool ShouldLookForGP) {
if (N.getOpcode() == ISD::ADD) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
(!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
GlobalAddressSDNode *GA =
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
if (Const && GA &&
(GA->getOpcode() == ISD::TargetGlobalAddress)) {
if ((N0.getOpcode() == HexagonISD::CONST32) &&
!hasNumUsesBelowThresGA(GA))
return false;
R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
Const->getDebugLoc(),
N.getValueType(),
GA->getOffset() +
(uint64_t)Const->getSExtValue());
return true;
}
}
}
return false;
}

127
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -690,30 +690,6 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
case Hexagon::STriw_abs_setimm_V4:
// V4 global address load.
case Hexagon::LDrid_GP_cPt_V4 :
case Hexagon::LDrid_GP_cNotPt_V4 :
case Hexagon::LDrid_GP_cdnPt_V4 :
case Hexagon::LDrid_GP_cdnNotPt_V4 :
case Hexagon::LDrib_GP_cPt_V4 :
case Hexagon::LDrib_GP_cNotPt_V4 :
case Hexagon::LDrib_GP_cdnPt_V4 :
case Hexagon::LDrib_GP_cdnNotPt_V4 :
case Hexagon::LDriub_GP_cPt_V4 :
case Hexagon::LDriub_GP_cNotPt_V4 :
case Hexagon::LDriub_GP_cdnPt_V4 :
case Hexagon::LDriub_GP_cdnNotPt_V4 :
case Hexagon::LDrih_GP_cPt_V4 :
case Hexagon::LDrih_GP_cNotPt_V4 :
case Hexagon::LDrih_GP_cdnPt_V4 :
case Hexagon::LDrih_GP_cdnNotPt_V4 :
case Hexagon::LDriuh_GP_cPt_V4 :
case Hexagon::LDriuh_GP_cNotPt_V4 :
case Hexagon::LDriuh_GP_cdnPt_V4 :
case Hexagon::LDriuh_GP_cdnNotPt_V4 :
case Hexagon::LDriw_GP_cPt_V4 :
case Hexagon::LDriw_GP_cNotPt_V4 :
case Hexagon::LDriw_GP_cdnPt_V4 :
case Hexagon::LDriw_GP_cdnNotPt_V4 :
case Hexagon::LDd_GP_cPt_V4 :
case Hexagon::LDd_GP_cNotPt_V4 :
case Hexagon::LDd_GP_cdnPt_V4 :
@ -740,22 +716,6 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
case Hexagon::LDw_GP_cdnNotPt_V4 :
// V4 global address store.
case Hexagon::STrid_GP_cPt_V4 :
case Hexagon::STrid_GP_cNotPt_V4 :
case Hexagon::STrid_GP_cdnPt_V4 :
case Hexagon::STrid_GP_cdnNotPt_V4 :
case Hexagon::STrib_GP_cPt_V4 :
case Hexagon::STrib_GP_cNotPt_V4 :
case Hexagon::STrib_GP_cdnPt_V4 :
case Hexagon::STrib_GP_cdnNotPt_V4 :
case Hexagon::STrih_GP_cPt_V4 :
case Hexagon::STrih_GP_cNotPt_V4 :
case Hexagon::STrih_GP_cdnPt_V4 :
case Hexagon::STrih_GP_cdnNotPt_V4 :
case Hexagon::STriw_GP_cPt_V4 :
case Hexagon::STriw_GP_cNotPt_V4 :
case Hexagon::STriw_GP_cdnPt_V4 :
case Hexagon::STriw_GP_cdnNotPt_V4 :
case Hexagon::STd_GP_cPt_V4 :
case Hexagon::STd_GP_cNotPt_V4 :
case Hexagon::STd_GP_cdnPt_V4 :
@ -774,18 +734,6 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
case Hexagon::STw_GP_cdnNotPt_V4 :
// V4 predicated global address new value store.
case Hexagon::STrib_GP_cPt_nv_V4 :
case Hexagon::STrib_GP_cNotPt_nv_V4 :
case Hexagon::STrib_GP_cdnPt_nv_V4 :
case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
case Hexagon::STrih_GP_cPt_nv_V4 :
case Hexagon::STrih_GP_cNotPt_nv_V4 :
case Hexagon::STrih_GP_cdnPt_nv_V4 :
case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
case Hexagon::STriw_GP_cPt_nv_V4 :
case Hexagon::STriw_GP_cNotPt_nv_V4 :
case Hexagon::STriw_GP_cdnPt_nv_V4 :
case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
case Hexagon::STb_GP_cPt_nv_V4 :
case Hexagon::STb_GP_cNotPt_nv_V4 :
case Hexagon::STb_GP_cdnPt_nv_V4 :
@ -1177,7 +1125,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STrib_indexed_nv_V4:
case Hexagon::STrib_indexed_shl_nv_V4:
case Hexagon::STrib_shl_nv_V4:
case Hexagon::STrib_GP_nv_V4:
case Hexagon::STb_GP_nv_V4:
case Hexagon::POST_STbri_nv_V4:
case Hexagon::STrib_cPt_nv_V4:
@ -1200,10 +1147,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STb_GP_cNotPt_nv_V4:
case Hexagon::STb_GP_cdnPt_nv_V4:
case Hexagon::STb_GP_cdnNotPt_nv_V4:
case Hexagon::STrib_GP_cPt_nv_V4:
case Hexagon::STrib_GP_cNotPt_nv_V4:
case Hexagon::STrib_GP_cdnPt_nv_V4:
case Hexagon::STrib_GP_cdnNotPt_nv_V4:
case Hexagon::STrib_abs_nv_V4:
case Hexagon::STrib_abs_cPt_nv_V4:
case Hexagon::STrib_abs_cdnPt_nv_V4:
@ -1220,7 +1163,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STrih_indexed_nv_V4:
case Hexagon::STrih_indexed_shl_nv_V4:
case Hexagon::STrih_shl_nv_V4:
case Hexagon::STrih_GP_nv_V4:
case Hexagon::STh_GP_nv_V4:
case Hexagon::POST_SThri_nv_V4:
case Hexagon::STrih_cPt_nv_V4:
@ -1243,10 +1185,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STh_GP_cNotPt_nv_V4:
case Hexagon::STh_GP_cdnPt_nv_V4:
case Hexagon::STh_GP_cdnNotPt_nv_V4:
case Hexagon::STrih_GP_cPt_nv_V4:
case Hexagon::STrih_GP_cNotPt_nv_V4:
case Hexagon::STrih_GP_cdnPt_nv_V4:
case Hexagon::STrih_GP_cdnNotPt_nv_V4:
case Hexagon::STrih_abs_nv_V4:
case Hexagon::STrih_abs_cPt_nv_V4:
case Hexagon::STrih_abs_cdnPt_nv_V4:
@ -1263,7 +1201,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STriw_indexed_nv_V4:
case Hexagon::STriw_indexed_shl_nv_V4:
case Hexagon::STriw_shl_nv_V4:
case Hexagon::STriw_GP_nv_V4:
case Hexagon::STw_GP_nv_V4:
case Hexagon::POST_STwri_nv_V4:
case Hexagon::STriw_cPt_nv_V4:
@ -1286,10 +1223,6 @@ bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
case Hexagon::STw_GP_cNotPt_nv_V4:
case Hexagon::STw_GP_cdnPt_nv_V4:
case Hexagon::STw_GP_cdnNotPt_nv_V4:
case Hexagon::STriw_GP_cPt_nv_V4:
case Hexagon::STriw_GP_cNotPt_nv_V4:
case Hexagon::STriw_GP_cdnPt_nv_V4:
case Hexagon::STriw_GP_cdnNotPt_nv_V4:
case Hexagon::STriw_abs_nv_V4:
case Hexagon::STriw_abs_cPt_nv_V4:
case Hexagon::STriw_abs_cdnPt_nv_V4:
@ -1732,26 +1665,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
case Hexagon::STw_GP_cNotPt_V4:
return Hexagon::STw_GP_cPt_V4;
case Hexagon::STrid_GP_cPt_V4:
return Hexagon::STrid_GP_cNotPt_V4;
case Hexagon::STrid_GP_cNotPt_V4:
return Hexagon::STrid_GP_cPt_V4;
case Hexagon::STrib_GP_cPt_V4:
return Hexagon::STrib_GP_cNotPt_V4;
case Hexagon::STrib_GP_cNotPt_V4:
return Hexagon::STrib_GP_cPt_V4;
case Hexagon::STrih_GP_cPt_V4:
return Hexagon::STrih_GP_cNotPt_V4;
case Hexagon::STrih_GP_cNotPt_V4:
return Hexagon::STrih_GP_cPt_V4;
case Hexagon::STriw_GP_cPt_V4:
return Hexagon::STriw_GP_cNotPt_V4;
case Hexagon::STriw_GP_cNotPt_V4:
return Hexagon::STriw_GP_cPt_V4;
// Load.
case Hexagon::LDrid_cPt:
return Hexagon::LDrid_cNotPt;
@ -2037,25 +1950,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
Hexagon::LDriw_indexed_shl_cNotPt_V4;
// V4 Load from global address
case Hexagon::LDrid_GP_V4:
return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
Hexagon::LDrid_GP_cNotPt_V4;
case Hexagon::LDrib_GP_V4:
return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
Hexagon::LDrib_GP_cNotPt_V4;
case Hexagon::LDriub_GP_V4:
return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
Hexagon::LDriub_GP_cNotPt_V4;
case Hexagon::LDrih_GP_V4:
return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
Hexagon::LDrih_GP_cNotPt_V4;
case Hexagon::LDriuh_GP_V4:
return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
Hexagon::LDriuh_GP_cNotPt_V4;
case Hexagon::LDriw_GP_V4:
return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
Hexagon::LDriw_GP_cNotPt_V4;
case Hexagon::LDd_GP_V4:
return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
Hexagon::LDd_GP_cNotPt_V4;
@ -2138,19 +2032,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
Hexagon::STrid_indexed_shl_cNotPt_V4;
// V4 Store to global address
case Hexagon::STrid_GP_V4:
return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
Hexagon::STrid_GP_cNotPt_V4;
case Hexagon::STrib_GP_V4:
return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
Hexagon::STrib_GP_cNotPt_V4;
case Hexagon::STrih_GP_V4:
return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
Hexagon::STrih_GP_cNotPt_V4;
case Hexagon::STriw_GP_V4:
return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
Hexagon::STriw_GP_cNotPt_V4;
case Hexagon::STd_GP_V4:
return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
Hexagon::STd_GP_cNotPt_V4;
@ -2867,14 +2748,6 @@ isConditionalStore (const MachineInstr* MI) const {
return QRI.Subtarget.hasV4TOps();
// V4 global address store before promoting to dot new.
case Hexagon::STrid_GP_cPt_V4 :
case Hexagon::STrid_GP_cNotPt_V4 :
case Hexagon::STrib_GP_cPt_V4 :
case Hexagon::STrib_GP_cNotPt_V4 :
case Hexagon::STrih_GP_cPt_V4 :
case Hexagon::STrih_GP_cNotPt_V4 :
case Hexagon::STriw_GP_cPt_V4 :
case Hexagon::STriw_GP_cNotPt_V4 :
case Hexagon::STd_GP_cPt_V4 :
case Hexagon::STd_GP_cNotPt_V4 :
case Hexagon::STb_GP_cPt_V4 :

754
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -21,6 +21,17 @@ def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
// Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
// Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
(HexagonCONST32 node:$addr), [{
return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
}]>;
// Hexagon V4 Architecture spec defines 8 instruction classes:
// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
// compiler)
@ -585,226 +596,6 @@ def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
Requires<[HasV4T]>;
}
/// Load from global offset
let isPredicable = 1, neverHasSideEffects = 1 in
def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memd(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memd(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memd(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memd(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memd(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memb(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memb(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memb(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memb(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memb(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memub(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memub(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memub(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memub(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memub(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memh(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memuh(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memuh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memuh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memuh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memuh(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
(ins globaladdress:$global, u16Imm:$offset),
"$dst=memw(#$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1) $dst=memw(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1) $dst=memw(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if ($src1.new) $dst=memw(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
"if (!$src1.new) $dst=memw(##$global+$offset)",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
(ins globaladdress:$global),
@ -1128,82 +919,6 @@ def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
(i32 (LDw_GP_V4 tglobaladdr:$global))>,
Requires<[HasV4T]>;
def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memd(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memub(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memuh(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memh(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memuh(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memw(#foo + x)
let AddedComplexity = 100 in
def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset))),
(i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
Requires<[HasV4T]>;
// zext i1->i64
def : Pat <(i64 (zext (i1 PredRegs:$src1))),
(i64 (COMBINE_Ir_V4 0, (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
@ -1649,163 +1364,6 @@ def STriw_shl_V4 : STInst<(outs),
// memw(Rx++Mu:brev)=Rt
// memw(gp+#u16:2)=Rt
/// store to global address
let isPredicable = 1, neverHasSideEffects = 1 in
def STrid_GP_V4 : STInst2<(outs),
(ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
"memd(#$global+$offset) = $src",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrid_GP_cPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
DoubleRegs:$src2),
"if ($src1) memd(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrid_GP_cNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
DoubleRegs:$src2),
"if (!$src1) memd(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrid_GP_cdnPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
DoubleRegs:$src2),
"if ($src1.new) memd(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
DoubleRegs:$src2),
"if (!$src1.new) memd(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def STrib_GP_V4 : STInst2<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memb(#$global+$offset) = $src",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrib_GP_cPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memb(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrib_GP_cNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memb(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrib_GP_cdnPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memb(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memb(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def STrih_GP_V4 : STInst2<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memh(#$global+$offset) = $src",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrih_GP_cPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memh(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrih_GP_cNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memh(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrih_GP_cdnPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memh(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memh(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let isPredicable = 1, neverHasSideEffects = 1 in
def STriw_GP_V4 : STInst2<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memw(#$global+$offset) = $src",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_GP_cPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memw(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_GP_cNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memw(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_GP_cdnPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memw(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memw(##$global+$offset) = $src2",
[]>,
Requires<[HasV4T]>;
// memd(#global)=Rtt
let isPredicable = 1, neverHasSideEffects = 1 in
@ -2024,72 +1582,6 @@ def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
(STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset),
(i64 DoubleRegs:$src1)),
(STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset),
(i32 IntRegs:$src1)),
(STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset),
(i32 IntRegs:$src1)),
(STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset),
(i32 IntRegs:$src1)),
(STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memd(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i64 DoubleRegs:$src1),
(add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei8 (i32 IntRegs:$src1),
(add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memh(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei16 (i32 IntRegs:$src1),
(add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memw(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i32 IntRegs:$src1),
(add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset)),
(STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
(i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
//===----------------------------------------------------------------------===
// ST -
//===----------------------------------------------------------------------===
@ -2269,14 +1761,6 @@ defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
// memb(Rx++Mu)=Nt.new
// memb(Rx++Mu:brev)=Nt.new
// memb(gp+#u16:0)=Nt.new
let mayStore = 1, neverHasSideEffects = 1 in
def STrib_GP_nv_V4 : NVInst_V4<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memb(#$global+$offset) = $src.new",
[]>,
Requires<[HasV4T]>;
// memb(#global)=Nt.new
let mayStore = 1, neverHasSideEffects = 1 in
def STb_GP_nv_V4 : NVInst_V4<(outs),
@ -2299,14 +1783,6 @@ def STrih_shl_nv_V4 : NVInst_V4<(outs),
// memh(Rx++Mu)=Nt.new
// memh(Rx++Mu:brev)=Nt.new
// memh(gp+#u16:1)=Nt.new
let mayStore = 1, neverHasSideEffects = 1 in
def STrih_GP_nv_V4 : NVInst_V4<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memh(#$global+$offset) = $src.new",
[]>,
Requires<[HasV4T]>;
// memh(#global)=Nt.new
let mayStore = 1, neverHasSideEffects = 1 in
def STh_GP_nv_V4 : NVInst_V4<(outs),
@ -2329,12 +1805,6 @@ def STriw_shl_nv_V4 : NVInst_V4<(outs),
// memw(Rx++Mu)=Nt.new
// memw(Rx++Mu:brev)=Nt.new
// memw(gp+#u16:2)=Nt.new
let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP_nv_V4 : NVInst_V4<(outs),
(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
"memw(#$global+$offset) = $src.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STw_GP_nv_V4 : NVInst_V4<(outs),
@ -2439,102 +1909,6 @@ def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memb(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memb(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memb(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memb(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memh(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memh(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memh(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memh(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1) memw(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1) memw(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if ($src1.new) memw(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
let mayStore = 1, neverHasSideEffects = 1 in
def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
IntRegs:$src2),
"if (!$src1.new) memw(##$global+$offset) = $src2.new",
[]>,
Requires<[HasV4T]>;
//===----------------------------------------------------------------------===//
// NV/ST -
//===----------------------------------------------------------------------===//
@ -4736,3 +4110,109 @@ def STrih_offset_ext_V4 : STInst<(outs),
[(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_1ImmPred:$src2))]>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memd(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i64 DoubleRegs:$src1),
FoldGlobalAddrGP:$addr),
(STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
(i64 DoubleRegs:$src1)),
(STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memh(#foo + x)
let AddedComplexity = 100 in
def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from store(globaladdress + x) -> memw(#foo + x)
let AddedComplexity = 100 in
def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
(STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
(STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memd(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
(i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
(i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
(i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memb(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
(i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
//let AddedComplexity = 100 in
let AddedComplexity = 100 in
def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
(i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memh(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
(i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memuh(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
(i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
(i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memub(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
(i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
(i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
// Map from load(globaladdress + x) -> memw(#foo + x)
let AddedComplexity = 100 in
def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
(i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
(i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -122,7 +122,7 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
bool HexagonPassConfig::addInstSelector() {
addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
addPass(createHexagonISelDag(getHexagonTargetMachine()));
addPass(createHexagonISelDag(getHexagonTargetMachine(), getOptLevel()));
addPass(createHexagonPeephole());
return false;
}

277
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -376,7 +376,6 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
case Hexagon::STrib_indexed:
case Hexagon::STrib_indexed_shl_V4:
case Hexagon::STrib_shl_V4:
case Hexagon::STrib_GP_V4:
case Hexagon::STb_GP_V4:
case Hexagon::POST_STbri:
case Hexagon::STrib_cPt:
@ -399,17 +398,12 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
case Hexagon::STb_GP_cNotPt_V4:
case Hexagon::STb_GP_cdnPt_V4:
case Hexagon::STb_GP_cdnNotPt_V4:
case Hexagon::STrib_GP_cPt_V4:
case Hexagon::STrib_GP_cNotPt_V4:
case Hexagon::STrib_GP_cdnPt_V4:
case Hexagon::STrib_GP_cdnNotPt_V4:
// store halfword
case Hexagon::STrih:
case Hexagon::STrih_indexed:
case Hexagon::STrih_indexed_shl_V4:
case Hexagon::STrih_shl_V4:
case Hexagon::STrih_GP_V4:
case Hexagon::STh_GP_V4:
case Hexagon::POST_SThri:
case Hexagon::STrih_cPt:
@ -432,17 +426,12 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
case Hexagon::STh_GP_cNotPt_V4:
case Hexagon::STh_GP_cdnPt_V4:
case Hexagon::STh_GP_cdnNotPt_V4:
case Hexagon::STrih_GP_cPt_V4:
case Hexagon::STrih_GP_cNotPt_V4:
case Hexagon::STrih_GP_cdnPt_V4:
case Hexagon::STrih_GP_cdnNotPt_V4:
// store word
case Hexagon::STriw:
case Hexagon::STriw_indexed:
case Hexagon::STriw_indexed_shl_V4:
case Hexagon::STriw_shl_V4:
case Hexagon::STriw_GP_V4:
case Hexagon::STw_GP_V4:
case Hexagon::POST_STwri:
case Hexagon::STriw_cPt:
@ -465,10 +454,6 @@ bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
case Hexagon::STw_GP_cNotPt_V4:
case Hexagon::STw_GP_cdnPt_V4:
case Hexagon::STw_GP_cdnNotPt_V4:
case Hexagon::STriw_GP_cPt_V4:
case Hexagon::STriw_GP_cNotPt_V4:
case Hexagon::STriw_GP_cdnPt_V4:
case Hexagon::STriw_GP_cdnNotPt_V4:
return QRI->Subtarget.hasV4TOps();
}
return false;
@ -508,9 +493,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STrib_shl_V4:
return Hexagon::STrib_shl_nv_V4;
case Hexagon::STrib_GP_V4:
return Hexagon::STrib_GP_nv_V4;
case Hexagon::STb_GP_V4:
return Hexagon::STb_GP_nv_V4;
@ -577,18 +559,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STb_GP_cdnNotPt_V4:
return Hexagon::STb_GP_cdnNotPt_nv_V4;
case Hexagon::STrib_GP_cPt_V4:
return Hexagon::STrib_GP_cPt_nv_V4;
case Hexagon::STrib_GP_cNotPt_V4:
return Hexagon::STrib_GP_cNotPt_nv_V4;
case Hexagon::STrib_GP_cdnPt_V4:
return Hexagon::STrib_GP_cdnPt_nv_V4;
case Hexagon::STrib_GP_cdnNotPt_V4:
return Hexagon::STrib_GP_cdnNotPt_nv_V4;
// store new value halfword
case Hexagon::STrih:
return Hexagon::STrih_nv_V4;
@ -602,9 +572,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STrih_shl_V4:
return Hexagon::STrih_shl_nv_V4;
case Hexagon::STrih_GP_V4:
return Hexagon::STrih_GP_nv_V4;
case Hexagon::STh_GP_V4:
return Hexagon::STh_GP_nv_V4;
@ -671,18 +638,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STh_GP_cdnNotPt_V4:
return Hexagon::STh_GP_cdnNotPt_nv_V4;
case Hexagon::STrih_GP_cPt_V4:
return Hexagon::STrih_GP_cPt_nv_V4;
case Hexagon::STrih_GP_cNotPt_V4:
return Hexagon::STrih_GP_cNotPt_nv_V4;
case Hexagon::STrih_GP_cdnPt_V4:
return Hexagon::STrih_GP_cdnPt_nv_V4;
case Hexagon::STrih_GP_cdnNotPt_V4:
return Hexagon::STrih_GP_cdnNotPt_nv_V4;
// store new value word
case Hexagon::STriw:
return Hexagon::STriw_nv_V4;
@ -696,9 +651,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STriw_shl_V4:
return Hexagon::STriw_shl_nv_V4;
case Hexagon::STriw_GP_V4:
return Hexagon::STriw_GP_nv_V4;
case Hexagon::STw_GP_V4:
return Hexagon::STw_GP_nv_V4;
@ -765,17 +717,6 @@ static int GetDotNewOp(const int opc) {
case Hexagon::STw_GP_cdnNotPt_V4:
return Hexagon::STw_GP_cdnNotPt_nv_V4;
case Hexagon::STriw_GP_cPt_V4:
return Hexagon::STriw_GP_cPt_nv_V4;
case Hexagon::STriw_GP_cNotPt_V4:
return Hexagon::STriw_GP_cNotPt_nv_V4;
case Hexagon::STriw_GP_cdnPt_V4:
return Hexagon::STriw_GP_cdnPt_nv_V4;
case Hexagon::STriw_GP_cdnNotPt_V4:
return Hexagon::STriw_GP_cdnNotPt_nv_V4;
}
}
@ -821,12 +762,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STb_GP_cNotPt_V4 :
return Hexagon::STb_GP_cdnNotPt_V4;
case Hexagon::STrib_GP_cPt_V4 :
return Hexagon::STrib_GP_cdnPt_V4;
case Hexagon::STrib_GP_cNotPt_V4 :
return Hexagon::STrib_GP_cdnNotPt_V4;
// Store doubleword conditionally
case Hexagon::STrid_cPt :
return Hexagon::STrid_cdnPt_V4;
@ -858,12 +793,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STd_GP_cNotPt_V4 :
return Hexagon::STd_GP_cdnNotPt_V4;
case Hexagon::STrid_GP_cPt_V4 :
return Hexagon::STrid_GP_cdnPt_V4;
case Hexagon::STrid_GP_cNotPt_V4 :
return Hexagon::STrid_GP_cdnNotPt_V4;
// Store halfword conditionally
case Hexagon::STrih_cPt :
return Hexagon::STrih_cdnPt_V4;
@ -901,12 +830,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STh_GP_cNotPt_V4 :
return Hexagon::STh_GP_cdnNotPt_V4;
case Hexagon::STrih_GP_cPt_V4 :
return Hexagon::STrih_GP_cdnPt_V4;
case Hexagon::STrih_GP_cNotPt_V4 :
return Hexagon::STrih_GP_cdnNotPt_V4;
// Store word conditionally
case Hexagon::STriw_cPt :
return Hexagon::STriw_cdnPt_V4;
@ -944,12 +867,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STw_GP_cNotPt_V4 :
return Hexagon::STw_GP_cdnNotPt_V4;
case Hexagon::STriw_GP_cPt_V4 :
return Hexagon::STriw_GP_cdnPt_V4;
case Hexagon::STriw_GP_cNotPt_V4 :
return Hexagon::STriw_GP_cdnNotPt_V4;
// Condtional Jumps
case Hexagon::JMP_c:
return Hexagon::JMP_cdnPt;
@ -1166,42 +1083,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::LDw_GP_cNotPt_V4:
return Hexagon::LDw_GP_cdnNotPt_V4;
case Hexagon::LDrid_GP_cPt_V4:
return Hexagon::LDrid_GP_cdnPt_V4;
case Hexagon::LDrid_GP_cNotPt_V4:
return Hexagon::LDrid_GP_cdnNotPt_V4;
case Hexagon::LDrib_GP_cPt_V4:
return Hexagon::LDrib_GP_cdnPt_V4;
case Hexagon::LDrib_GP_cNotPt_V4:
return Hexagon::LDrib_GP_cdnNotPt_V4;
case Hexagon::LDriub_GP_cPt_V4:
return Hexagon::LDriub_GP_cdnPt_V4;
case Hexagon::LDriub_GP_cNotPt_V4:
return Hexagon::LDriub_GP_cdnNotPt_V4;
case Hexagon::LDrih_GP_cPt_V4:
return Hexagon::LDrih_GP_cdnPt_V4;
case Hexagon::LDrih_GP_cNotPt_V4:
return Hexagon::LDrih_GP_cdnNotPt_V4;
case Hexagon::LDriuh_GP_cPt_V4:
return Hexagon::LDriuh_GP_cdnPt_V4;
case Hexagon::LDriuh_GP_cNotPt_V4:
return Hexagon::LDriuh_GP_cdnNotPt_V4;
case Hexagon::LDriw_GP_cPt_V4:
return Hexagon::LDriw_GP_cdnPt_V4;
case Hexagon::LDriw_GP_cNotPt_V4:
return Hexagon::LDriw_GP_cdnNotPt_V4;
// Conditional store new-value byte
case Hexagon::STrib_cPt_nv_V4 :
return Hexagon::STrib_cdnPt_nv_V4;
@ -1229,12 +1110,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STb_GP_cNotPt_nv_V4 :
return Hexagon::STb_GP_cdnNotPt_nv_V4;
case Hexagon::STrib_GP_cPt_nv_V4 :
return Hexagon::STrib_GP_cdnPt_nv_V4;
case Hexagon::STrib_GP_cNotPt_nv_V4 :
return Hexagon::STrib_GP_cdnNotPt_nv_V4;
// Conditional store new-value halfword
case Hexagon::STrih_cPt_nv_V4 :
return Hexagon::STrih_cdnPt_nv_V4;
@ -1262,12 +1137,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STh_GP_cNotPt_nv_V4 :
return Hexagon::STh_GP_cdnNotPt_nv_V4;
case Hexagon::STrih_GP_cPt_nv_V4 :
return Hexagon::STrih_GP_cdnPt_nv_V4;
case Hexagon::STrih_GP_cNotPt_nv_V4 :
return Hexagon::STrih_GP_cdnNotPt_nv_V4;
// Conditional store new-value word
case Hexagon::STriw_cPt_nv_V4 :
return Hexagon::STriw_cdnPt_nv_V4;
@ -1295,12 +1164,6 @@ static int GetDotNewPredOp(const int opc) {
case Hexagon::STw_GP_cNotPt_nv_V4 :
return Hexagon::STw_GP_cdnNotPt_nv_V4;
case Hexagon::STriw_GP_cPt_nv_V4 :
return Hexagon::STriw_GP_cdnPt_nv_V4;
case Hexagon::STriw_GP_cNotPt_nv_V4 :
return Hexagon::STriw_GP_cdnNotPt_nv_V4;
// Conditional add
case Hexagon::ADD_ri_cPt :
return Hexagon::ADD_ri_cdnPt;
@ -1661,42 +1524,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::LDw_GP_cdnNotPt_V4:
return Hexagon::LDw_GP_cNotPt_V4;
case Hexagon::LDrid_GP_cdnPt_V4:
return Hexagon::LDrid_GP_cPt_V4;
case Hexagon::LDrid_GP_cdnNotPt_V4:
return Hexagon::LDrid_GP_cNotPt_V4;
case Hexagon::LDrib_GP_cdnPt_V4:
return Hexagon::LDrib_GP_cPt_V4;
case Hexagon::LDrib_GP_cdnNotPt_V4:
return Hexagon::LDrib_GP_cNotPt_V4;
case Hexagon::LDriub_GP_cdnPt_V4:
return Hexagon::LDriub_GP_cPt_V4;
case Hexagon::LDriub_GP_cdnNotPt_V4:
return Hexagon::LDriub_GP_cNotPt_V4;
case Hexagon::LDrih_GP_cdnPt_V4:
return Hexagon::LDrih_GP_cPt_V4;
case Hexagon::LDrih_GP_cdnNotPt_V4:
return Hexagon::LDrih_GP_cNotPt_V4;
case Hexagon::LDriuh_GP_cdnPt_V4:
return Hexagon::LDriuh_GP_cPt_V4;
case Hexagon::LDriuh_GP_cdnNotPt_V4:
return Hexagon::LDriuh_GP_cNotPt_V4;
case Hexagon::LDriw_GP_cdnPt_V4:
return Hexagon::LDriw_GP_cPt_V4;
case Hexagon::LDriw_GP_cdnNotPt_V4:
return Hexagon::LDriw_GP_cNotPt_V4;
// Conditional add
case Hexagon::ADD_ri_cdnPt :
@ -1830,16 +1657,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STb_GP_cNotPt_nv_V4:
return Hexagon::STb_GP_cNotPt_V4;
case Hexagon::STrib_GP_cdnPt_nv_V4:
case Hexagon::STrib_GP_cdnPt_V4:
case Hexagon::STrib_GP_cPt_nv_V4:
return Hexagon::STrib_GP_cPt_V4;
case Hexagon::STrib_GP_cdnNotPt_nv_V4:
case Hexagon::STrib_GP_cdnNotPt_V4:
case Hexagon::STrib_GP_cNotPt_nv_V4:
return Hexagon::STrib_GP_cNotPt_V4;
// Store new-value byte - unconditional
case Hexagon::STrib_nv_V4:
return Hexagon::STrib;
@ -1853,9 +1670,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STrib_shl_nv_V4:
return Hexagon::STrib_shl_V4;
case Hexagon::STrib_GP_nv_V4:
return Hexagon::STrib_GP_V4;
case Hexagon::STb_GP_nv_V4:
return Hexagon::STb_GP_V4;
@ -1919,16 +1733,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STh_GP_cNotPt_nv_V4:
return Hexagon::STh_GP_cNotPt_V4;
case Hexagon::STrih_GP_cdnPt_nv_V4:
case Hexagon::STrih_GP_cdnPt_V4:
case Hexagon::STrih_GP_cPt_nv_V4:
return Hexagon::STrih_GP_cPt_V4;
case Hexagon::STrih_GP_cdnNotPt_nv_V4:
case Hexagon::STrih_GP_cdnNotPt_V4:
case Hexagon::STrih_GP_cNotPt_nv_V4:
return Hexagon::STrih_GP_cNotPt_V4;
// Store new-value halfword - unconditional
case Hexagon::STrih_nv_V4:
@ -1943,9 +1747,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STrih_shl_nv_V4:
return Hexagon::STrih_shl_V4;
case Hexagon::STrih_GP_nv_V4:
return Hexagon::STrih_GP_V4;
case Hexagon::STh_GP_nv_V4:
return Hexagon::STh_GP_V4;
@ -2010,16 +1811,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STw_GP_cNotPt_nv_V4:
return Hexagon::STw_GP_cNotPt_V4;
case Hexagon::STriw_GP_cdnPt_nv_V4:
case Hexagon::STriw_GP_cdnPt_V4:
case Hexagon::STriw_GP_cPt_nv_V4:
return Hexagon::STriw_GP_cPt_V4;
case Hexagon::STriw_GP_cdnNotPt_nv_V4:
case Hexagon::STriw_GP_cdnNotPt_V4:
case Hexagon::STriw_GP_cNotPt_nv_V4:
return Hexagon::STriw_GP_cNotPt_V4;
// Store new-value word - unconditional
case Hexagon::STriw_nv_V4:
@ -2034,9 +1825,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STriw_shl_nv_V4:
return Hexagon::STriw_shl_V4;
case Hexagon::STriw_GP_nv_V4:
return Hexagon::STriw_GP_V4;
case Hexagon::STw_GP_nv_V4:
return Hexagon::STw_GP_V4;
@ -2075,11 +1863,6 @@ static int GetDotOldOp(const int opc) {
case Hexagon::STd_GP_cdnNotPt_V4 :
return Hexagon::STd_GP_cNotPt_V4;
case Hexagon::STrid_GP_cdnPt_V4 :
return Hexagon::STrid_GP_cPt_V4;
case Hexagon::STrid_GP_cdnNotPt_V4 :
return Hexagon::STrid_GP_cNotPt_V4;
}
}
@ -2215,42 +1998,22 @@ static bool GetPredicateSense(MachineInstr* MI,
case Hexagon::ZXTB_cdnPt_V4 :
case Hexagon::ZXTH_cPt_V4 :
case Hexagon::ZXTH_cdnPt_V4 :
case Hexagon::LDrid_GP_cPt_V4 :
case Hexagon::LDrib_GP_cPt_V4 :
case Hexagon::LDriub_GP_cPt_V4 :
case Hexagon::LDrih_GP_cPt_V4 :
case Hexagon::LDriuh_GP_cPt_V4 :
case Hexagon::LDriw_GP_cPt_V4 :
case Hexagon::LDd_GP_cPt_V4 :
case Hexagon::LDb_GP_cPt_V4 :
case Hexagon::LDub_GP_cPt_V4 :
case Hexagon::LDh_GP_cPt_V4 :
case Hexagon::LDuh_GP_cPt_V4 :
case Hexagon::LDw_GP_cPt_V4 :
case Hexagon::STrid_GP_cPt_V4 :
case Hexagon::STrib_GP_cPt_V4 :
case Hexagon::STrih_GP_cPt_V4 :
case Hexagon::STriw_GP_cPt_V4 :
case Hexagon::STd_GP_cPt_V4 :
case Hexagon::STb_GP_cPt_V4 :
case Hexagon::STh_GP_cPt_V4 :
case Hexagon::STw_GP_cPt_V4 :
case Hexagon::LDrid_GP_cdnPt_V4 :
case Hexagon::LDrib_GP_cdnPt_V4 :
case Hexagon::LDriub_GP_cdnPt_V4 :
case Hexagon::LDrih_GP_cdnPt_V4 :
case Hexagon::LDriuh_GP_cdnPt_V4 :
case Hexagon::LDriw_GP_cdnPt_V4 :
case Hexagon::LDd_GP_cdnPt_V4 :
case Hexagon::LDb_GP_cdnPt_V4 :
case Hexagon::LDub_GP_cdnPt_V4 :
case Hexagon::LDh_GP_cdnPt_V4 :
case Hexagon::LDuh_GP_cdnPt_V4 :
case Hexagon::LDw_GP_cdnPt_V4 :
case Hexagon::STrid_GP_cdnPt_V4 :
case Hexagon::STrib_GP_cdnPt_V4 :
case Hexagon::STrih_GP_cdnPt_V4 :
case Hexagon::STriw_GP_cdnPt_V4 :
case Hexagon::STd_GP_cdnPt_V4 :
case Hexagon::STb_GP_cdnPt_V4 :
case Hexagon::STh_GP_cdnPt_V4 :
@ -2375,42 +2138,22 @@ static bool GetPredicateSense(MachineInstr* MI,
case Hexagon::ZXTH_cNotPt_V4 :
case Hexagon::ZXTH_cdnNotPt_V4 :
case Hexagon::LDrid_GP_cNotPt_V4 :
case Hexagon::LDrib_GP_cNotPt_V4 :
case Hexagon::LDriub_GP_cNotPt_V4 :
case Hexagon::LDrih_GP_cNotPt_V4 :
case Hexagon::LDriuh_GP_cNotPt_V4 :
case Hexagon::LDriw_GP_cNotPt_V4 :
case Hexagon::LDd_GP_cNotPt_V4 :
case Hexagon::LDb_GP_cNotPt_V4 :
case Hexagon::LDub_GP_cNotPt_V4 :
case Hexagon::LDh_GP_cNotPt_V4 :
case Hexagon::LDuh_GP_cNotPt_V4 :
case Hexagon::LDw_GP_cNotPt_V4 :
case Hexagon::STrid_GP_cNotPt_V4 :
case Hexagon::STrib_GP_cNotPt_V4 :
case Hexagon::STrih_GP_cNotPt_V4 :
case Hexagon::STriw_GP_cNotPt_V4 :
case Hexagon::STd_GP_cNotPt_V4 :
case Hexagon::STb_GP_cNotPt_V4 :
case Hexagon::STh_GP_cNotPt_V4 :
case Hexagon::STw_GP_cNotPt_V4 :
case Hexagon::LDrid_GP_cdnNotPt_V4 :
case Hexagon::LDrib_GP_cdnNotPt_V4 :
case Hexagon::LDriub_GP_cdnNotPt_V4 :
case Hexagon::LDrih_GP_cdnNotPt_V4 :
case Hexagon::LDriuh_GP_cdnNotPt_V4 :
case Hexagon::LDriw_GP_cdnNotPt_V4 :
case Hexagon::LDd_GP_cdnNotPt_V4 :
case Hexagon::LDb_GP_cdnNotPt_V4 :
case Hexagon::LDub_GP_cdnNotPt_V4 :
case Hexagon::LDh_GP_cdnNotPt_V4 :
case Hexagon::LDuh_GP_cdnNotPt_V4 :
case Hexagon::LDw_GP_cdnNotPt_V4 :
case Hexagon::STrid_GP_cdnNotPt_V4 :
case Hexagon::STrib_GP_cdnNotPt_V4 :
case Hexagon::STrih_GP_cdnNotPt_V4 :
case Hexagon::STriw_GP_cdnNotPt_V4 :
case Hexagon::STd_GP_cdnNotPt_V4 :
case Hexagon::STb_GP_cdnNotPt_V4 :
case Hexagon::STh_GP_cdnNotPt_V4 :
@ -2572,27 +2315,7 @@ bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
case Hexagon::LDuh_GP_cdnNotPt_V4:
case Hexagon::LDw_GP_cdnPt_V4:
case Hexagon::LDw_GP_cdnNotPt_V4:
case Hexagon::LDrid_GP_cdnPt_V4:
case Hexagon::LDrid_GP_cdnNotPt_V4:
case Hexagon::LDrib_GP_cdnPt_V4:
case Hexagon::LDrib_GP_cdnNotPt_V4:
case Hexagon::LDriub_GP_cdnPt_V4:
case Hexagon::LDriub_GP_cdnNotPt_V4:
case Hexagon::LDrih_GP_cdnPt_V4:
case Hexagon::LDrih_GP_cdnNotPt_V4:
case Hexagon::LDriuh_GP_cdnPt_V4:
case Hexagon::LDriuh_GP_cdnNotPt_V4:
case Hexagon::LDriw_GP_cdnPt_V4:
case Hexagon::LDriw_GP_cdnNotPt_V4:
case Hexagon::STrid_GP_cdnPt_V4:
case Hexagon::STrid_GP_cdnNotPt_V4:
case Hexagon::STrib_GP_cdnPt_V4:
case Hexagon::STrib_GP_cdnNotPt_V4:
case Hexagon::STrih_GP_cdnPt_V4:
case Hexagon::STrih_GP_cdnNotPt_V4:
case Hexagon::STriw_GP_cdnPt_V4:
case Hexagon::STriw_GP_cdnNotPt_V4:
case Hexagon::STd_GP_cdnPt_V4:
case Hexagon::STd_GP_cdnNotPt_V4:
case Hexagon::STb_GP_cdnPt_V4:

51
llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll Normal file
View File

@ -0,0 +1,51 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we generate load instructions with global + offset
%struct.struc = type { i8, i8, i16, i32 }
@foo = common global %struct.struc zeroinitializer, align 4
define void @loadWord(i32 %val1, i32 %val2, i32* nocapture %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##foo{{ *}}+{{ *}}4)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%0 = load i32* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 3), align 4
store i32 %0, i32* %ival, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @loadByte(i32 %val1, i32 %val2, i8* nocapture %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(##foo{{ *}}+{{ *}}1)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%0 = load i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1
store i8 %0, i8* %ival, align 1
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @loadHWord(i32 %val1, i32 %val2, i16* %ival) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(##foo{{ *}}+{{ *}}2)
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%0 = load i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2
store i16 %0, i16* %ival, align 2
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}

35
llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll Normal file
View File

@ -0,0 +1,35 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we generate store instructions with global + offset
%struct.struc = type { i8, i8, i16, i32 }
@foo = common global %struct.struc zeroinitializer, align 4
define void @storeByte(i32 %val1, i32 %val2, i8 zeroext %ival) nounwind {
; CHECK: memb(##foo{{ *}}+{{ *}}1){{ *}}={{ *}}r{{[0-9]+}}
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
store i8 %ival, i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @storeHW(i32 %val1, i32 %val2, i16 signext %ival) nounwind {
; CHECK: memh(##foo{{ *}}+{{ *}}2){{ *}}={{ *}}r{{[0-9]+}}
entry:
%cmp = icmp sgt i32 %val1, %val2
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
store i16 %ival, i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}