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[mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3. 

Summary:
Previously, attempting to extract lanes 2 and 3 would actually extract lane 1.
The MSA CodeGen tests only covered lanes 0 and 1.

Differential Revision: http://llvm-reviews.chandlerc.com/D2935

llvm-svn: 202848
This commit is contained in:
Daniel Sanders 2014-03-04 13:54:30 +00:00
parent d964e7cd81
commit d920770add
2 changed files with 19 additions and 1 deletions
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2
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -2755,7 +2755,7 @@ emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
else { else {
unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
} }

18
llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
View File

@ -137,6 +137,24 @@ define float @extract_v4f32_elt0() nounwind {
; MIPS32: .size extract_v4f32_elt0 ; MIPS32: .size extract_v4f32_elt0
} }
define float @extract_v4f32_elt2() nounwind {
; MIPS32: extract_v4f32_elt2:
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 2
; Element 2 can be obtained by splatting it across the vector and extracting
; $w0:sub_lo
; MIPS32-DAG: splati.w $w0, [[R1]][2]
ret float %3
; MIPS32: .size extract_v4f32_elt2
}
define double @extract_v2f64() nounwind { define double @extract_v2f64() nounwind {
; MIPS32: extract_v2f64: ; MIPS32: extract_v2f64: