forked from OSchip/llvm-project
parent
15ecfbf1f6
commit
d9198907a6
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@ -72,9 +72,8 @@ class DispatchStage final : public Stage {
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public:
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DispatchStage(const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
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unsigned MaxDispatchWidth, RetireControlUnit &R,
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RegisterFile &F)
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const llvm::MCRegisterInfo &MRI, unsigned MaxDispatchWidth,
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RetireControlUnit &R, RegisterFile &F)
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: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
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CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) {}
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@ -42,8 +42,8 @@ Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
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// Create the pipeline stages.
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auto Fetch = llvm::make_unique<FetchStage>(IB, SrcMgr);
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auto Dispatch = llvm::make_unique<DispatchStage>(
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STI, MRI, Opts.RegisterFileSize, Opts.DispatchWidth, *RCU, *PRF);
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auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
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*RCU, *PRF);
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auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
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auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
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