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80 columns. 

llvm-svn: 180040
This commit is contained in:
Akira Hatanaka 2013-04-22 20:13:37 +00:00
parent 0d6964cf4a
commit d8fb032cff
3 changed files with 9 additions and 6 deletions
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6
llvm/lib/Target/Mips/Mips16ISelLowering.cpp
View File

@ -613,7 +613,8 @@ MachineBasicBlock
unsigned regX = MI->getOperand(0).getReg();
unsigned regY = MI->getOperand(1).getReg();
MachineBasicBlock *target = MI->getOperand(2).getMBB();
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
.addReg(regY);
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
@ -635,7 +636,8 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
CmpOpc = CmpiXOpc;
else
llvm_unreachable("immediate field not usable");
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
.addImm(imm);
BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;

2
llvm/lib/Target/Mips/MipsOs16.cpp
View File

@ -1,4 +1,4 @@
//===---- MipsOs16.cpp for Mips Option -Os16 --------===//
//===---- MipsOs16.cpp for Mips Option -Os16 --------===//
//
// The LLVM Compiler Infrastructure
//

7
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -131,7 +131,8 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
DAG);
case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
}
@ -328,8 +329,8 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
if (!BV ||
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize,
!Subtarget->isLittle()) ||
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
EltSize,!Subtarget->isLittle()) ||
(SplatBitSize != EltSize) ||
!isUIntN(Log2_32(EltSize), SplatValue.getZExtValue()))
return SDValue();