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[ARM] Expand vector ctlz_zero_undef so it becomes ctlz. 

The default is Legal, which results in 'Cannot select' errors.

llvm-svn: 267521
This commit is contained in:
Craig Topper 2016-04-26 05:04:37 +00:00
parent edb4a6ba98
commit d8d6be4f99
2 changed files with 72 additions and 0 deletions
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10
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -583,6 +583,16 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i8, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i16, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v1i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
// NEON does not have single instruction CTTZ for vectors.
setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);

62
llvm/test/CodeGen/ARM/vcnt.ll
View File

@ -82,6 +82,68 @@ define <2 x i64> @vclzQ64(<2 x i64>* %A) nounwind {
ret <2 x i64> %tmp2
}
define <8 x i8> @vclz8b(<8 x i8>* %A) nounwind {
;CHECK-LABEL: vclz8b:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 1)
ret <8 x i8> %tmp2
}
define <4 x i16> @vclz16b(<4 x i16>* %A) nounwind {
;CHECK-LABEL: vclz16b:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 1)
ret <4 x i16> %tmp2
}
define <2 x i32> @vclz32b(<2 x i32>* %A) nounwind {
;CHECK-LABEL: vclz32b:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 1)
ret <2 x i32> %tmp2
}
define <1 x i64> @vclz64b(<1 x i64>* %A) nounwind {
;CHECK-LABEL: vclz64b:
%tmp1 = load <1 x i64>, <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 1)
ret <1 x i64> %tmp2
}
define <16 x i8> @vclzQ8b(<16 x i8>* %A) nounwind {
;CHECK-LABEL: vclzQ8b:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 1)
ret <16 x i8> %tmp2
}
define <8 x i16> @vclzQ16b(<8 x i16>* %A) nounwind {
;CHECK-LABEL: vclzQ16b:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 1)
ret <8 x i16> %tmp2
}
define <4 x i32> @vclzQ32b(<4 x i32>* %A) nounwind {
;CHECK-LABEL: vclzQ32b:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 1)
ret <4 x i32> %tmp2
}
define <2 x i64> @vclzQ64b(<2 x i64>* %A) nounwind {
;CHECK-LABEL: vclzQ64b:
%tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 1)
ret <2 x i64> %tmp2
}
declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone