forked from OSchip/llvm-project
[X86] AMD Zen 3: throughput for renameable GPR moves is 6
They are resolved at the register rename stage without using any execution units.
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@ -1442,9 +1442,9 @@ defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not
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// Zero Cycle Move
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///////////////////////////////////////////////////////////////////////////////
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def Zn3WriteMoveRenameable : SchedWriteRes<[Zn3ALU0123]> {
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def Zn3WriteMoveRenameable : SchedWriteRes<[]> {
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let Latency = 0;
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let ResourceCycles = [1];
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let ResourceCycles = [];
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let NumMicroOps = 1;
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}
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def : InstRW<[Zn3WriteMoveRenameable], (instrs MOV32rr, MOV32rr_REV,
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@ -81,7 +81,7 @@ xchgq %r15, %rax
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# CHECK: Dispatch Width: 6
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# CHECK-NEXT: uOps Per Cycle: 6.00
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# CHECK-NEXT: IPC: 6.00
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# CHECK-NEXT: Block RThroughput: 3.5
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# CHECK-NEXT: Block RThroughput: 2.3
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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@ -92,20 +92,20 @@ xchgq %r15, %rax
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 0 0.25 movl %eax, %ecx
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# CHECK-NEXT: 1 0 0.25 movl %ecx, %edx
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# CHECK-NEXT: 1 0 0.25 movl %edx, %ebp
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# CHECK-NEXT: 1 0 0.25 movl %ebp, %esi
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# CHECK-NEXT: 1 0 0.25 movl %esi, %edi
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# CHECK-NEXT: 1 0 0.25 movl %edi, %r8d
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# CHECK-NEXT: 1 0 0.25 movl %r8d, %r9d
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# CHECK-NEXT: 1 0 0.25 movl %r9d, %r10d
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# CHECK-NEXT: 1 0 0.25 movl %r10d, %r11d
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# CHECK-NEXT: 1 0 0.25 movl %r11d, %r12d
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# CHECK-NEXT: 1 0 0.25 movl %r12d, %r13d
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# CHECK-NEXT: 1 0 0.25 movl %r13d, %r14d
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# CHECK-NEXT: 1 0 0.25 movl %r14d, %r15d
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# CHECK-NEXT: 1 0 0.25 movl %r15d, %eax
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# CHECK-NEXT: 1 0 0.17 movl %eax, %ecx
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# CHECK-NEXT: 1 0 0.17 movl %ecx, %edx
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# CHECK-NEXT: 1 0 0.17 movl %edx, %ebp
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# CHECK-NEXT: 1 0 0.17 movl %ebp, %esi
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# CHECK-NEXT: 1 0 0.17 movl %esi, %edi
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# CHECK-NEXT: 1 0 0.17 movl %edi, %r8d
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# CHECK-NEXT: 1 0 0.17 movl %r8d, %r9d
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# CHECK-NEXT: 1 0 0.17 movl %r9d, %r10d
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# CHECK-NEXT: 1 0 0.17 movl %r10d, %r11d
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# CHECK-NEXT: 1 0 0.17 movl %r11d, %r12d
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# CHECK-NEXT: 1 0 0.17 movl %r12d, %r13d
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# CHECK-NEXT: 1 0 0.17 movl %r13d, %r14d
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# CHECK-NEXT: 1 0 0.17 movl %r14d, %r15d
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# CHECK-NEXT: 1 0 0.17 movl %r15d, %eax
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# CHECK: Register File statistics:
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# CHECK-NEXT: Total number of mappings created: 0
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@ -349,7 +349,7 @@ xchgq %r15, %rax
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# CHECK: Dispatch Width: 6
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# CHECK-NEXT: uOps Per Cycle: 6.00
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# CHECK-NEXT: IPC: 6.00
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# CHECK-NEXT: Block RThroughput: 3.5
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# CHECK-NEXT: Block RThroughput: 2.3
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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@ -360,20 +360,20 @@ xchgq %r15, %rax
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 0 0.25 movq %rax, %rcx
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# CHECK-NEXT: 1 0 0.25 movq %rcx, %rdx
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# CHECK-NEXT: 1 0 0.25 movq %rdx, %rbp
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# CHECK-NEXT: 1 0 0.25 movq %rbp, %rsi
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# CHECK-NEXT: 1 0 0.25 movq %rsi, %rdi
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# CHECK-NEXT: 1 0 0.25 movq %rdi, %r8
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# CHECK-NEXT: 1 0 0.25 movq %r8, %r9
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# CHECK-NEXT: 1 0 0.25 movq %r9, %r10
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# CHECK-NEXT: 1 0 0.25 movq %r10, %r11
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# CHECK-NEXT: 1 0 0.25 movq %r11, %r12
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# CHECK-NEXT: 1 0 0.25 movq %r12, %r13
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# CHECK-NEXT: 1 0 0.25 movq %r13, %r14
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# CHECK-NEXT: 1 0 0.25 movq %r14, %r15
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# CHECK-NEXT: 1 0 0.25 movq %r15, %rax
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# CHECK-NEXT: 1 0 0.17 movq %rax, %rcx
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# CHECK-NEXT: 1 0 0.17 movq %rcx, %rdx
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# CHECK-NEXT: 1 0 0.17 movq %rdx, %rbp
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# CHECK-NEXT: 1 0 0.17 movq %rbp, %rsi
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# CHECK-NEXT: 1 0 0.17 movq %rsi, %rdi
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# CHECK-NEXT: 1 0 0.17 movq %rdi, %r8
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# CHECK-NEXT: 1 0 0.17 movq %r8, %r9
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# CHECK-NEXT: 1 0 0.17 movq %r9, %r10
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# CHECK-NEXT: 1 0 0.17 movq %r10, %r11
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# CHECK-NEXT: 1 0 0.17 movq %r11, %r12
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# CHECK-NEXT: 1 0 0.17 movq %r12, %r13
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# CHECK-NEXT: 1 0 0.17 movq %r13, %r14
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# CHECK-NEXT: 1 0 0.17 movq %r14, %r15
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# CHECK-NEXT: 1 0 0.17 movq %r15, %rax
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# CHECK: Register File statistics:
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# CHECK-NEXT: Total number of mappings created: 0
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