[X86] AMD Zen 3: throughput for renameable GPR moves is 6

They are resolved at the register rename stage without
using any execution units.
This commit is contained in:
Roman Lebedev 2021-05-07 15:11:14 +03:00
parent c3cd8ed009
commit d8c6202576
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GPG Key ID: 083C3EBB4A1689E0
2 changed files with 32 additions and 32 deletions

View File

@ -1442,9 +1442,9 @@ defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not
// Zero Cycle Move
///////////////////////////////////////////////////////////////////////////////
def Zn3WriteMoveRenameable : SchedWriteRes<[Zn3ALU0123]> {
def Zn3WriteMoveRenameable : SchedWriteRes<[]> {
let Latency = 0;
let ResourceCycles = [1];
let ResourceCycles = [];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMoveRenameable], (instrs MOV32rr, MOV32rr_REV,

View File

@ -81,7 +81,7 @@ xchgq %r15, %rax
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 6.00
# CHECK-NEXT: IPC: 6.00
# CHECK-NEXT: Block RThroughput: 3.5
# CHECK-NEXT: Block RThroughput: 2.3
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@ -92,20 +92,20 @@ xchgq %r15, %rax
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 0 0.25 movl %eax, %ecx
# CHECK-NEXT: 1 0 0.25 movl %ecx, %edx
# CHECK-NEXT: 1 0 0.25 movl %edx, %ebp
# CHECK-NEXT: 1 0 0.25 movl %ebp, %esi
# CHECK-NEXT: 1 0 0.25 movl %esi, %edi
# CHECK-NEXT: 1 0 0.25 movl %edi, %r8d
# CHECK-NEXT: 1 0 0.25 movl %r8d, %r9d
# CHECK-NEXT: 1 0 0.25 movl %r9d, %r10d
# CHECK-NEXT: 1 0 0.25 movl %r10d, %r11d
# CHECK-NEXT: 1 0 0.25 movl %r11d, %r12d
# CHECK-NEXT: 1 0 0.25 movl %r12d, %r13d
# CHECK-NEXT: 1 0 0.25 movl %r13d, %r14d
# CHECK-NEXT: 1 0 0.25 movl %r14d, %r15d
# CHECK-NEXT: 1 0 0.25 movl %r15d, %eax
# CHECK-NEXT: 1 0 0.17 movl %eax, %ecx
# CHECK-NEXT: 1 0 0.17 movl %ecx, %edx
# CHECK-NEXT: 1 0 0.17 movl %edx, %ebp
# CHECK-NEXT: 1 0 0.17 movl %ebp, %esi
# CHECK-NEXT: 1 0 0.17 movl %esi, %edi
# CHECK-NEXT: 1 0 0.17 movl %edi, %r8d
# CHECK-NEXT: 1 0 0.17 movl %r8d, %r9d
# CHECK-NEXT: 1 0 0.17 movl %r9d, %r10d
# CHECK-NEXT: 1 0 0.17 movl %r10d, %r11d
# CHECK-NEXT: 1 0 0.17 movl %r11d, %r12d
# CHECK-NEXT: 1 0 0.17 movl %r12d, %r13d
# CHECK-NEXT: 1 0 0.17 movl %r13d, %r14d
# CHECK-NEXT: 1 0 0.17 movl %r14d, %r15d
# CHECK-NEXT: 1 0 0.17 movl %r15d, %eax
# CHECK: Register File statistics:
# CHECK-NEXT: Total number of mappings created: 0
@ -349,7 +349,7 @@ xchgq %r15, %rax
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 6.00
# CHECK-NEXT: IPC: 6.00
# CHECK-NEXT: Block RThroughput: 3.5
# CHECK-NEXT: Block RThroughput: 2.3
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@ -360,20 +360,20 @@ xchgq %r15, %rax
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 0 0.25 movq %rax, %rcx
# CHECK-NEXT: 1 0 0.25 movq %rcx, %rdx
# CHECK-NEXT: 1 0 0.25 movq %rdx, %rbp
# CHECK-NEXT: 1 0 0.25 movq %rbp, %rsi
# CHECK-NEXT: 1 0 0.25 movq %rsi, %rdi
# CHECK-NEXT: 1 0 0.25 movq %rdi, %r8
# CHECK-NEXT: 1 0 0.25 movq %r8, %r9
# CHECK-NEXT: 1 0 0.25 movq %r9, %r10
# CHECK-NEXT: 1 0 0.25 movq %r10, %r11
# CHECK-NEXT: 1 0 0.25 movq %r11, %r12
# CHECK-NEXT: 1 0 0.25 movq %r12, %r13
# CHECK-NEXT: 1 0 0.25 movq %r13, %r14
# CHECK-NEXT: 1 0 0.25 movq %r14, %r15
# CHECK-NEXT: 1 0 0.25 movq %r15, %rax
# CHECK-NEXT: 1 0 0.17 movq %rax, %rcx
# CHECK-NEXT: 1 0 0.17 movq %rcx, %rdx
# CHECK-NEXT: 1 0 0.17 movq %rdx, %rbp
# CHECK-NEXT: 1 0 0.17 movq %rbp, %rsi
# CHECK-NEXT: 1 0 0.17 movq %rsi, %rdi
# CHECK-NEXT: 1 0 0.17 movq %rdi, %r8
# CHECK-NEXT: 1 0 0.17 movq %r8, %r9
# CHECK-NEXT: 1 0 0.17 movq %r9, %r10
# CHECK-NEXT: 1 0 0.17 movq %r10, %r11
# CHECK-NEXT: 1 0 0.17 movq %r11, %r12
# CHECK-NEXT: 1 0 0.17 movq %r12, %r13
# CHECK-NEXT: 1 0 0.17 movq %r13, %r14
# CHECK-NEXT: 1 0 0.17 movq %r14, %r15
# CHECK-NEXT: 1 0 0.17 movq %r15, %rax
# CHECK: Register File statistics:
# CHECK-NEXT: Total number of mappings created: 0