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R600: Simplify stream outputs intrinsic 

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 173296
This commit is contained in:
Tom Stellard 2013-01-23 21:39:47 +00:00
parent aa300017e1
commit d8ac91d436
5 changed files with 13 additions and 47 deletions
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32
llvm/lib/Target/R600/R600ISelLowering.cpp
View File

@ -386,39 +386,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
Chain);
}
case AMDGPUIntrinsic::R600_store_stream_output : {
MachineFunction &MF = DAG.getMachineFunction();
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
int64_t BufIndex = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
SDNode **OutputsMap = MFI->StreamOutputs[BufIndex];
unsigned Inst;
switch (cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue() ) {
// STREAM3
case 3:
Inst = 4;
break;
// STREAM2
case 2:
Inst = 3;
break;
// STREAM1
case 1:
Inst = 2;
break;
// STREAM0
case 0:
Inst = 1;
break;
default:
llvm_unreachable("Wrong buffer id for stream outputs !");
}
return InsertScalarToRegisterExport(DAG, Op.getDebugLoc(), OutputsMap,
RegIndex / 4, RegIndex % 4, Inst, 0, Op.getOperand(2),
Chain);
}
// default for switch(IntrinsicID)
default: break;
}

24
llvm/lib/Target/R600/R600Instructions.td
View File

@ -604,24 +604,24 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
multiclass SteamOutputExportPattern<Instruction ExportInst,
bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
// Stream0
def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
(i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
4095, imm:$mask, buf0inst, 0)>;
// Stream1
def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 2),
(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
(i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
4095, imm:$mask, buf1inst, 0)>;
// Stream2
def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 3),
(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
(i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
4095, imm:$mask, buf2inst, 0)>;
// Stream3
def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 4),
(i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
(i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
(ExportInst R600_Reg128:$src, 0, imm:$arraybase,
4095, imm:$mask, buf3inst, 0)>;
}

2
llvm/lib/Target/R600/R600Intrinsics.td
View File

@ -20,7 +20,7 @@ let TargetPrefix = "R600", isTarget = 1 in {
def int_R600_load_input_linear :
Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
def int_R600_store_stream_output :
Intrinsic<[], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>;
Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
def int_R600_store_pixel_color :
Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
def int_R600_store_pixel_depth :

1
llvm/lib/Target/R600/R600MachineFunctionInfo.cpp
View File

@ -17,7 +17,6 @@ R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
HasLinearInterpolation(false),
HasPerspectiveInterpolation(false) {
memset(Outputs, 0, sizeof(Outputs));
memset(StreamOutputs, 0, sizeof(StreamOutputs));
}
unsigned R600MachineFunctionInfo::GetIJPerspectiveIndex() const {

1
llvm/lib/Target/R600/R600MachineFunctionInfo.h
View File

@ -25,7 +25,6 @@ public:
R600MachineFunctionInfo(const MachineFunction &MF);
std::vector<unsigned> ReservedRegs;
SDNode *Outputs[16];
SDNode *StreamOutputs[64][4];
bool HasLinearInterpolation;
bool HasPerspectiveInterpolation;