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Get rid of a few calls through the subtarget to get the ABI 

that's actually sitting on the target machine.

llvm-svn: 227513
This commit is contained in:
Eric Christopher 2015-01-29 23:27:45 +00:00
parent 96e72c6ab1
commit d86af63a46
3 changed files with 15 additions and 15 deletions
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13
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -691,6 +691,7 @@ printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
bool IsABICalls = Subtarget->isABICalls(); bool IsABICalls = Subtarget->isABICalls();
const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
if (IsABICalls) { if (IsABICalls) {
getTargetStreamer().emitDirectiveAbiCalls(); getTargetStreamer().emitDirectiveAbiCalls();
Reloc::Model RM = TM.getRelocationModel(); Reloc::Model RM = TM.getRelocationModel();
@ -698,7 +699,7 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// Ideally it should test for properties of the ABI and not the ABI // Ideally it should test for properties of the ABI and not the ABI
// itself. // itself.
// For the moment, I'm only correcting enough to make MIPS-IV work. // For the moment, I'm only correcting enough to make MIPS-IV work.
if (RM == Reloc::Static && !Subtarget->isABI_N64()) if (RM == Reloc::Static && !ABI.IsN64())
getTargetStreamer().emitDirectiveOptionPic0(); getTargetStreamer().emitDirectiveOptionPic0();
} }
@ -715,7 +716,7 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// TODO: handle O64 ABI // TODO: handle O64 ABI
if (Subtarget->isABI_EABI()) { if (ABI.IsEABI()) {
if (Subtarget->isGP32bit()) if (Subtarget->isGP32bit())
OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long32", OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long32",
ELF::SHT_PROGBITS, 0)); ELF::SHT_PROGBITS, 0));
@ -729,17 +730,15 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// We should always emit a '.module fp=...' but binutils 2.24 does not accept // We should always emit a '.module fp=...' but binutils 2.24 does not accept
// it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
// -mfp64) and omit it otherwise. // -mfp64) and omit it otherwise.
if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() || if (ABI.IsO32() && (Subtarget->isABI_FPXX() || Subtarget->isFP64bit()))
Subtarget->isFP64bit()))
getTargetStreamer().emitDirectiveModuleFP(); getTargetStreamer().emitDirectiveModuleFP();
// We should always emit a '.module [no]oddspreg' but binutils 2.24 does not // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
// accept it. We therefore emit it when it contradicts the default or an // accept it. We therefore emit it when it contradicts the default or an
// option has changed the default (i.e. FPXX) and omit it otherwise. // option has changed the default (i.e. FPXX) and omit it otherwise.
if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() || if (ABI.IsO32() && (!Subtarget->useOddSPReg() || Subtarget->isABI_FPXX()))
Subtarget->isABI_FPXX()))
getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(), getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
Subtarget->isABI_O32()); ABI.IsO32());
} }
void MipsAsmPrinter::emitInlineAsmStart( void MipsAsmPrinter::emitInlineAsmStart(

5
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@ -162,9 +162,10 @@ public:
TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext(); Context = &funcInfo.Fn->getContext();
TargetSupported = ((TM.getRelocationModel() == Reloc::PIC_) && TargetSupported =
((TM.getRelocationModel() == Reloc::PIC_) &&
((Subtarget->hasMips32r2() || Subtarget->hasMips32()) && ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
(Subtarget->isABI_O32()))); (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
UnsupportedFPMode = Subtarget->isFP64bit(); UnsupportedFPMode = Subtarget->isFP64bit();
} }

10
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -134,13 +134,13 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
const TargetRegisterClass *RC; const TargetRegisterClass *RC;
const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
V0 = RegInfo.createVirtualRegister(RC); V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC); V1 = RegInfo.createVirtualRegister(RC);
if (Subtarget->isABI_N64()) { if (ABI.IsN64()) {
MF.getRegInfo().addLiveIn(Mips::T9_64); MF.getRegInfo().addLiveIn(Mips::T9_64);
MBB.addLiveIn(Mips::T9_64); MBB.addLiveIn(Mips::T9_64);
@ -172,7 +172,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
MF.getRegInfo().addLiveIn(Mips::T9); MF.getRegInfo().addLiveIn(Mips::T9);
MBB.addLiveIn(Mips::T9); MBB.addLiveIn(Mips::T9);
if (Subtarget->isABI_N32()) { if (ABI.IsN32()) {
// lui $v0, %hi(%neg(%gp_rel(fname))) // lui $v0, %hi(%neg(%gp_rel(fname)))
// addu $v1, $v0, $t9 // addu $v1, $v0, $t9
// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
@ -185,7 +185,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
return; return;
} }
assert(Subtarget->isABI_O32()); assert(ABI.IsO32());
// For O32 ABI, the following instruction sequence is emitted to initialize // For O32 ABI, the following instruction sequence is emitted to initialize
// the global base register: // the global base register: