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[PowerPC] Eliminate integer compare instructions - vol. 5 

Adds handling for i64 SETNE comparison (both sign and zero extended).

Differential Revision: https://reviews.llvm.org/D33720

llvm-svn: 304907
This commit is contained in:
Nemanja Ivanovic 2017-06-07 13:18:06 +00:00
parent 3c039d968e
commit d8623f0825
6 changed files with 593 additions and 6 deletions
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26
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -2907,6 +2907,19 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
getI64Imm(58, dl), getI64Imm(63, dl)),
0);
}
case ISD::SETNE: {
// {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
// (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA)
// {addcz.reg, addcz.CA} = (addcarry %a, -1)
// (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA)
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue AC =
SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
Xor, getI32Imm(~0U, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
Xor, AC.getValue(1)), 0);
}
}
}
@ -2931,6 +2944,19 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
Addic, Addic.getValue(1)), 0);
}
case ISD::SETNE: {
// {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b))
// (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA)
// {subfcz.reg, subfcz.CA} = (subcarry 0, %a)
// (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA)
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue SC =
SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
Xor, getI32Imm(0, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
SC, SC.getValue(1)), 0);
}
}
}

73
llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
View File

@ -40,8 +40,8 @@ return: ; preds = %if.end, %if.then
ret i32 %retval.0
}
define void @neg_truncate_i32(i32 *%ptr) {
; CHECK-LABEL: neg_truncate_i32:
define void @neg_truncate_i32_eq(i32 *%ptr) {
; CHECK-LABEL: neg_truncate_i32_eq:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
; CHECK-NEXT: rldicl. r3, r3, 0, 63
@ -66,8 +66,8 @@ if.end29: ; preds = %if.else
}
; Function Attrs: nounwind
define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: logic_ne_64:
define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: logic_eq_64:
; CHECK: xor r7, r3, r4
; CHECK-NEXT: li r6, 55
; CHECK-NEXT: xor r5, r5, r6
@ -99,8 +99,8 @@ return: ; preds = %if.end, %if.then
ret i64 %retval.0
}
define void @neg_truncate_i64(i64 *%ptr) {
; CHECK-LABEL: neg_truncate_i64:
define void @neg_truncate_i64_eq(i64 *%ptr) {
; CHECK-LABEL: neg_truncate_i64_eq:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: rldicl. r3, r3, 0, 63
@ -124,6 +124,67 @@ if.end29: ; preds = %if.else
}
; Function Attrs: nounwind
define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
; CHECK-LABEL: logic_ne_64:
; CHECK: xor r7, r3, r4
; CHECK-NEXT: li r6, 55
; CHECK-NEXT: addic r8, r7, -1
; CHECK-NEXT: xor r5, r5, r6
; CHECK-NEXT: subfe r7, r8, r7
; CHECK-NEXT: cntlzd r5, r5
; CHECK-NEXT: addic r12, r4, -1
; CHECK-NEXT: rldicl r5, r5, 58, 63
; CHECK-NEXT: subfe r6, r12, r4
; CHECK-NEXT: and r6, r7, r6
; CHECK-NEXT: or. r5, r6, r5
; CHECK-NEXT: bc 4, 1
entry:
%tobool = icmp ne i64 %a, %b
%tobool1 = icmp ne i64 %b, 0
%or.cond = and i1 %tobool, %tobool1
%tobool3 = icmp eq i64 %c, 55
%or.cond5 = or i1 %or.cond, %tobool3
br i1 %or.cond5, label %if.end, label %if.then
if.then: ; preds = %entry
%call = tail call i64 @foo64(i64 %a) #2
br label %return
if.end: ; preds = %entry
%call4 = tail call i64 @bar64(i64 %b) #2
br label %return
return: ; preds = %if.end, %if.then
%retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
ret i64 %retval.0
}
define void @neg_truncate_i64_ne(i64 *%ptr) {
; CHECK-LABEL: neg_truncate_i64_ne:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: andi. r3, r3, 1
; CHECK-NEXT: bclr 12, 1, 0
; CHECK-NEXT: # BB#1: # %if.end29.thread136
; CHECK-NEXT: .LBB5_2: # %if.end29
entry:
%0 = load i64, i64* %ptr, align 4
%rem17127 = and i64 %0, 1
%cmp18 = icmp ne i64 %rem17127, 0
br label %if.else
if.else: ; preds = %entry
br i1 %cmp18, label %if.end29, label %if.end29.thread136
if.end29.thread136: ; preds = %if.else
unreachable
if.end29: ; preds = %if.else
ret void
}
declare signext i32 @foo(i32 signext)
declare signext i32 @bar(i32 signext)
declare i64 @foo64(i64)

125
llvm/test/CodeGen/PowerPC/testComparesinesll.ll Normal file
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@ -0,0 +1,125 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_inesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesll_z(i64 %a) {
; CHECK-LABEL: test_inesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesll_sext_z(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

125
llvm/test/CodeGen/PowerPC/testComparesineull.ll Normal file
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@ -0,0 +1,125 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ineull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineull_z(i64 %a) {
; CHECK-LABEL: test_ineull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineull_sext_z(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

125
llvm/test/CodeGen/PowerPC/testComparesllnesll.ll Normal file
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@ -0,0 +1,125 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llnesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_z(i64 %a) {
; CHECK-LABEL: test_llnesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_sext_z(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llnesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

125
llvm/test/CodeGen/PowerPC/testComparesllneull.ll Normal file
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@ -0,0 +1,125 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llneull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_z(i64 %a) {
; CHECK-LABEL: test_llneull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext_z(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}