forked from OSchip/llvm-project
[PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
This commit is contained in:
Ulrich Weigand
parent
640192daa8
commit
d839490f16
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@ -136,6 +136,9 @@ class PPCAsmParser : public MCTargetAsmParser {
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm);
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void ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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/// @name Auto-generated Match Functions
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/// {
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@ -413,6 +416,59 @@ void PPCOperand::print(raw_ostream &OS) const {
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}
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void PPCAsmParser::
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ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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case PPC::SLWI: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLWINM);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(MCOperand::CreateImm(31 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::SRWI: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLWINM);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(32 - N));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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TmpInst.addOperand(MCOperand::CreateImm(31));
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Inst = TmpInst;
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break;
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}
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case PPC::SLDI: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLDICR);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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TmpInst.addOperand(MCOperand::CreateImm(63 - N));
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Inst = TmpInst;
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break;
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}
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case PPC::SRDI: {
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MCInst TmpInst;
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int64_t N = Inst.getOperand(2).getImm();
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TmpInst.setOpcode(PPC::RLDICL);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateImm(64 - N));
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TmpInst.addOperand(MCOperand::CreateImm(N));
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Inst = TmpInst;
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break;
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}
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}
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}
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bool PPCAsmParser::
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MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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@ -423,6 +479,8 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
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default: break;
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case Match_Success:
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// Post-process instructions (typically extended mnemonics)
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ProcessInstruction(Inst, Operands);
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Inst.setLoc(IDLoc);
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Out.EmitInstruction(Inst);
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return false;
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@ -2111,3 +2111,87 @@ def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
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include "PPCInstrAltivec.td"
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include "PPCInstr64Bit.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Assembler Instruction Aliases
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//
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class PPCAsmPseudo<string asm, dag iops>
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: Instruction {
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let Namespace = "PPC";
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bit PPC64 = 0; // Default value, override with isPPC64
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let OutOperandList = (outs);
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let InOperandList = iops;
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let Pattern = [];
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let AsmString = asm;
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let isAsmParserOnly = 1;
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let isPseudo = 1;
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}
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def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
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def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
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(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
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def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
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def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
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(ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
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def : InstAlias<"blt $cc, $dst", (BCC 12, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bgt $cc, $dst", (BCC 44, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"beq $cc, $dst", (BCC 76, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bun $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bso $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bge $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bnl $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"ble $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bng $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bne $cc, $dst", (BCC 68, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bnu $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bns $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
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def : InstAlias<"bltlr $cc", (BCLR 12, crrc:$cc)>;
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def : InstAlias<"bgtlr $cc", (BCLR 44, crrc:$cc)>;
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def : InstAlias<"beqlr $cc", (BCLR 76, crrc:$cc)>;
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def : InstAlias<"bunlr $cc", (BCLR 108, crrc:$cc)>;
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def : InstAlias<"bsolr $cc", (BCLR 108, crrc:$cc)>;
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def : InstAlias<"bgelr $cc", (BCLR 4, crrc:$cc)>;
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def : InstAlias<"bnllr $cc", (BCLR 4, crrc:$cc)>;
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def : InstAlias<"blelr $cc", (BCLR 36, crrc:$cc)>;
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def : InstAlias<"bnglr $cc", (BCLR 36, crrc:$cc)>;
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def : InstAlias<"bnelr $cc", (BCLR 68, crrc:$cc)>;
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def : InstAlias<"bnulr $cc", (BCLR 100, crrc:$cc)>;
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def : InstAlias<"bnslr $cc", (BCLR 100, crrc:$cc)>;
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def : InstAlias<"bltctr $cc", (BCCTR 12, crrc:$cc)>;
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def : InstAlias<"bgtctr $cc", (BCCTR 44, crrc:$cc)>;
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def : InstAlias<"beqctr $cc", (BCCTR 76, crrc:$cc)>;
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def : InstAlias<"bunctr $cc", (BCCTR 108, crrc:$cc)>;
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def : InstAlias<"bsoctr $cc", (BCCTR 108, crrc:$cc)>;
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def : InstAlias<"bgectr $cc", (BCCTR 4, crrc:$cc)>;
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def : InstAlias<"bnlctr $cc", (BCCTR 4, crrc:$cc)>;
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def : InstAlias<"blectr $cc", (BCCTR 36, crrc:$cc)>;
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def : InstAlias<"bngctr $cc", (BCCTR 36, crrc:$cc)>;
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def : InstAlias<"bnectr $cc", (BCCTR 68, crrc:$cc)>;
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def : InstAlias<"bnuctr $cc", (BCCTR 100, crrc:$cc)>;
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def : InstAlias<"bnsctr $cc", (BCCTR 100, crrc:$cc)>;
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def : InstAlias<"bltctrl $cc", (BCCTRL 12, crrc:$cc)>;
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def : InstAlias<"bgtctrl $cc", (BCCTRL 44, crrc:$cc)>;
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def : InstAlias<"beqctrl $cc", (BCCTRL 76, crrc:$cc)>;
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def : InstAlias<"bunctrl $cc", (BCCTRL 108, crrc:$cc)>;
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def : InstAlias<"bsoctrl $cc", (BCCTRL 108, crrc:$cc)>;
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def : InstAlias<"bgectrl $cc", (BCCTRL 4, crrc:$cc)>;
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def : InstAlias<"bnlctrl $cc", (BCCTRL 4, crrc:$cc)>;
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def : InstAlias<"blectrl $cc", (BCCTRL 36, crrc:$cc)>;
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def : InstAlias<"bngctrl $cc", (BCCTRL 36, crrc:$cc)>;
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def : InstAlias<"bnectrl $cc", (BCCTRL 68, crrc:$cc)>;
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def : InstAlias<"bnuctrl $cc", (BCCTRL 100, crrc:$cc)>;
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def : InstAlias<"bnsctrl $cc", (BCCTRL 100, crrc:$cc)>;
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@ -0,0 +1,331 @@
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
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# FIXME: Condition register bit symbols
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# Branch mnemonics
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# CHECK: blr # encoding: [0x4e,0x80,0x00,0x20]
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blr
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# CHECK: bctr # encoding: [0x4e,0x80,0x04,0x20]
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bctr
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# FIXME: blrl
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# CHECK: bctrl # encoding: [0x4e,0x80,0x04,0x21]
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bctrl
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# FIXME: bt 2, target
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# FIXME: bta 2, target
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# FIXME: btlr 2
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# FIXME: btctr 2
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# FIXME: btl 2, target
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# FIXME: btla 2, target
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# FIXME: btlrl 2
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# FIXME: btctrl 2
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# FIXME: bf 2, target
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# FIXME: bfa 2, target
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# FIXME: bflr 2
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# FIXME: bfctr 2
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# FIXME: bfl 2, target
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# FIXME: bfla 2, target
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# FIXME: bflrl 2
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# FIXME: bfctrl 2
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# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdnz target
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# FIXME: bdnza target
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# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20]
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bdnzlr
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# FIXME: bdnzl target
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# FIXME: bdnzla target
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# FIXME: bdnzlrl
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# FIXME: bdnzt 2, target
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# FIXME: bdnzta 2, target
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# FIXME: bdnztlr 2
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# FIXME: bdnztl 2, target
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# FIXME: bdnztla 2, target
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# FIXME: bdnztlrl 2
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# FIXME: bdnzf 2, target
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# FIXME: bdnzfa 2, target
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# FIXME: bdnzflr 2
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# FIXME: bdnzfl 2, target
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# FIXME: bdnzfla 2, target
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# FIXME: bdnzflrl 2
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# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bdz target
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# FIXME: bdza target
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# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20]
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bdzlr
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# FIXME: bdzl target
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# FIXME: bdzla target
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# FIXME: bdzlrl
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# FIXME: bdzt 2, target
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# FIXME: bdzta 2, target
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# FIXME: bdztlr 2
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# FIXME: bdztl 2, target
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# FIXME: bdztla 2, target
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# FIXME: bdztlrl 2
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# FIXME: bdzf 2, target
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# FIXME: bdzfa 2, target
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# FIXME: bdzflr 2
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# FIXME: bdzfl 2, target
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# FIXME: bdzfla 2, target
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# FIXME: bdzflrl 2
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# CHECK: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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blt 2, target
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# FIXME: blta 2, target
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# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20]
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bltlr 2
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# CHECK: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20]
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bltctr 2
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# FIXME: bltl 2, target
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# FIXME: bltla 2, target
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# FIXME: bltlrl 2
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# CHECK: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21]
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bltctrl 2
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# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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ble 2, target
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# FIXME: blea 2, target
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# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
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blelr 2
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# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
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blectr 2
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# FIXME: blel 2, target
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# FIXME: blela 2, target
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# FIXME: blelrl 2
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# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
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blectrl 2
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# CHECK: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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beq 2, target
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# FIXME: beqa 2, target
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# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20]
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beqlr 2
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# CHECK: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20]
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beqctr 2
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# FIXME: beql 2, target
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# FIXME: beqla 2, target
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# FIXME: beqlrl 2
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# CHECK: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21]
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beqctrl 2
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# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bge 2, target
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# FIXME: bgea 2, target
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# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
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bgelr 2
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# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
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bgectr 2
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# FIXME: bgel 2, target
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# FIXME: bgela 2, target
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# FIXME: bgelrl 2
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# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
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bgectrl 2
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# CHECK: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bgt 2, target
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# FIXME: bgta 2, target
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# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20]
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bgtlr 2
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# CHECK: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20]
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bgtctr 2
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# FIXME: bgtl 2, target
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# FIXME: bgtla 2, target
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# FIXME: bgtlrl 2
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# CHECK: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21]
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bgtctrl 2
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# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bnl 2, target
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# FIXME: bnla 2, target
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# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20]
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bnllr 2
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# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20]
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bnlctr 2
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# FIXME: bnll 2, target
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# FIXME: bnlla 2, target
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# FIXME: bnllrl 2
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# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21]
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bnlctrl 2
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# CHECK: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bne 2, target
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# FIXME: bnea 2, target
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# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20]
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bnelr 2
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# CHECK: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20]
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bnectr 2
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# FIXME: bnel 2, target
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# FIXME: bnela 2, target
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# FIXME: bnelrl 2
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# CHECK: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21]
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bnectrl 2
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# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
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bng 2, target
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# FIXME: bnga 2, target
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# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20]
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bnglr 2
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# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20]
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bngctr 2
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# FIXME: bngl 2, target
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# FIXME: bngla 2, target
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# FIXME: bnglrl 2
|
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# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21]
|
||||
bngctrl 2
|
||||
|
||||
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
|
||||
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
||||
bso 2, target
|
||||
# FIXME: bsoa 2, target
|
||||
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
|
||||
bsolr 2
|
||||
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
|
||||
bsoctr 2
|
||||
# FIXME: bsol 2, target
|
||||
# FIXME: bsola 2, target
|
||||
# FIXME: bsolrl 2
|
||||
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
|
||||
bsoctrl 2
|
||||
|
||||
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
|
||||
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
||||
bns 2, target
|
||||
# FIXME: bnsa 2, target
|
||||
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
|
||||
bnslr 2
|
||||
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
|
||||
bnsctr 2
|
||||
# FIXME: bnsl 2, target
|
||||
# FIXME: bnsla 2, target
|
||||
# FIXME: bnslrl 2
|
||||
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
|
||||
bnsctrl 2
|
||||
|
||||
# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00]
|
||||
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
||||
bun 2, target
|
||||
# FIXME: buna 2, target
|
||||
# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20]
|
||||
bunlr 2
|
||||
# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20]
|
||||
bunctr 2
|
||||
# FIXME: bunl 2, target
|
||||
# FIXME: bunla 2, target
|
||||
# FIXME: bunlrl 2
|
||||
# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21]
|
||||
bunctrl 2
|
||||
|
||||
# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00]
|
||||
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
|
||||
bnu 2, target
|
||||
# FIXME: bnua 2, target
|
||||
# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20]
|
||||
bnulr 2
|
||||
# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20]
|
||||
bnuctr 2
|
||||
# FIXME: bnul 2, target
|
||||
# FIXME: bnula 2, target
|
||||
# FIXME: bnulrl 2
|
||||
# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21]
|
||||
bnuctrl 2
|
||||
|
||||
# FIXME: Condition register logical mnemonics
|
||||
|
||||
# FIXME: Subtract mnemonics
|
||||
|
||||
# Compare mnemonics
|
||||
|
||||
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
|
||||
cmpdi 2, 3, 128
|
||||
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
|
||||
cmpd 2, 3, 4
|
||||
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
|
||||
cmpldi 2, 3, 128
|
||||
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
|
||||
cmpld 2, 3, 4
|
||||
|
||||
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
|
||||
cmpwi 2, 3, 128
|
||||
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
|
||||
cmpw 2, 3, 4
|
||||
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
|
||||
cmplwi 2, 3, 128
|
||||
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
|
||||
cmplw 2, 3, 4
|
||||
|
||||
# FIXME: Trap mnemonics
|
||||
|
||||
# Rotate and shift mnemonics
|
||||
|
||||
# FIXME: extldi 2, 3, 4, 5
|
||||
# FIXME: extrdi 2, 3, 4, 5
|
||||
# FIXME: insrdi 2, 3, 4, 5
|
||||
# FIXME: rotldi 2, 3, 4
|
||||
# FIXME: rotrdi 2, 3, 4
|
||||
# FIXME: rotld 2, 3, 4
|
||||
# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4]
|
||||
sldi 2, 3, 4
|
||||
# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02]
|
||||
srdi 2, 3, 4
|
||||
# FIXME: clrldi 2, 3, 4
|
||||
# FIXME: clrrdi 2, 3, 4
|
||||
# FIXME: clrlsldi 2, 3, 4, 5
|
||||
|
||||
# FIXME: extlwi 2, 3, 4, 5
|
||||
# FIXME: extrwi 2, 3, 4, 5
|
||||
# FIXME: inslwi 2, 3, 4, 5
|
||||
# FIXME: insrwi 2, 3, 4, 5
|
||||
# FIXME: rotlwi 2, 3, 4
|
||||
# FIXME: rotrwi 2, 3, 4
|
||||
# FIXME: rotlw 2, 3, 4
|
||||
# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36]
|
||||
slwi 2, 3, 4
|
||||
# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e]
|
||||
srwi 2, 3, 4
|
||||
# FIXME: clrlwi 2, 3, 4
|
||||
# FIXME: clrrwi 2, 3, 4
|
||||
# FIXME: clrlslwi 2, 3, 4, 5
|
||||
|
||||
# Move to/from special purpose register mnemonics
|
||||
|
||||
# FIXME: mtxer 2
|
||||
# FIXME: mfxer 2
|
||||
# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6]
|
||||
mtlr 2
|
||||
# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6]
|
||||
mflr 2
|
||||
# CHECK: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6]
|
||||
mtctr 2
|
||||
# CHECK: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6]
|
||||
mfctr 2
|
||||
|
||||
# Miscellaneous mnemonics
|
||||
|
||||
# CHECK: nop # encoding: [0x60,0x00,0x00,0x00]
|
||||
nop
|
||||
# FIXME: xnop
|
||||
# CHECK: li 2, 128 # encoding: [0x38,0x40,0x00,0x80]
|
||||
li 2, 128
|
||||
# CHECK: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80]
|
||||
lis 2, 128
|
||||
# FIXME: la 2, 128(4)
|
||||
# CHECK: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78]
|
||||
mr 2, 3
|
||||
# FIXME: not 2, 3
|
||||
|
||||
Loading…
Reference in New Issue