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Thumb parsing and encoding for STM. 

llvm-svn: 138345
This commit is contained in:
Jim Grosbach 2011-08-23 18:15:37 +00:00
parent 169b2be611
commit d80d169a04
3 changed files with 26 additions and 0 deletions
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7
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3149,6 +3149,13 @@ validateInstruction(MCInst &Inst,
"registers must be in range r0-r7 or lr"); "registers must be in range r0-r7 or lr");
break; break;
} }
case ARM::tSTMIA_UPD: {
bool listContainsBase;
if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
return Error(Operands[4]->getStartLoc(),
"registers must be in range r0-r7");
break;
}
} }
return false; return false;

10
llvm/test/MC/ARM/basic-thumb-instructions.s
View File

@ -425,3 +425,13 @@ _func:
@ CHECK: setend be @ encoding: [0x58,0xb6] @ CHECK: setend be @ encoding: [0x58,0xb6]
@ CHECK: setend le @ encoding: [0x50,0xb6] @ CHECK: setend le @ encoding: [0x50,0xb6]
@------------------------------------------------------------------------------
@ STM
@------------------------------------------------------------------------------
stm r1!, {r2, r6}
stm r1!, {r1, r2, r3, r7}
@ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1]
@ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1]

9
llvm/test/MC/ARM/thumb-diagnostics.s
View File

@ -68,6 +68,15 @@ error: invalid operand for instruction
@ CHECK-ERRORS: ^ @ CHECK-ERRORS: ^
@ Invalid writeback and register lists for STM
stm r1, {r2, r6}
stm r1!, {r2, r9}
@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
@ CHECK-ERRORS: stm r1, {r2, r6}
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: registers must be in range r0-r7
@ CHECK-ERRORS: stm r1!, {r2, r9}
@ CHECK-ERRORS: ^
@ Out of range immediates for LSL instruction. @ Out of range immediates for LSL instruction.
lsls r4, r5, #-1 lsls r4, r5, #-1