forked from OSchip/llvm-project
parent
169b2be611
commit
d80d169a04
llvm
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@ -3149,6 +3149,13 @@ validateInstruction(MCInst &Inst,
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"registers must be in range r0-r7 or lr");
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break;
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}
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case ARM::tSTMIA_UPD: {
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bool listContainsBase;
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if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
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return Error(Operands[4]->getStartLoc(),
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"registers must be in range r0-r7");
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break;
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}
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}
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return false;
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@ -425,3 +425,13 @@ _func:
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@ CHECK: setend be @ encoding: [0x58,0xb6]
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@ CHECK: setend le @ encoding: [0x50,0xb6]
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@------------------------------------------------------------------------------
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@ STM
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@------------------------------------------------------------------------------
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stm r1!, {r2, r6}
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stm r1!, {r1, r2, r3, r7}
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@ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1]
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@ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1]
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@ -68,6 +68,15 @@ error: invalid operand for instruction
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@ CHECK-ERRORS: ^
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@ Invalid writeback and register lists for STM
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stm r1, {r2, r6}
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stm r1!, {r2, r9}
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@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
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@ CHECK-ERRORS: stm r1, {r2, r6}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: stm r1!, {r2, r9}
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@ CHECK-ERRORS: ^
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@ Out of range immediates for LSL instruction.
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lsls r4, r5, #-1
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