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Fix MSVC "32-bit shift implicitly converted to 64 bits" warnings. NFCI. 

llvm-svn: 371302
This commit is contained in:
Simon Pilgrim 2019-09-07 11:04:04 +00:00
parent 395f254bf0
commit d7d8bb937a
2 changed files with 2 additions and 2 deletions
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2
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -1420,7 +1420,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
setPrefLoopAlignment(
llvm::Align(1UL << Subtarget->getPrefLoopLogAlignment()));
llvm::Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
setMinFunctionAlignment(Subtarget->isThumb() ? llvm::Align(2)
: llvm::Align(4));

2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1893,7 +1893,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
MaxLoadsPerMemcmpOptSize = 2;
// Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
setPrefLoopAlignment(llvm::Align(1UL << ExperimentalPrefLoopAlignment));
setPrefLoopAlignment(llvm::Align(1ULL << ExperimentalPrefLoopAlignment));
// An out-of-order CPU can speculatively execute past a predictable branch,
// but a conditional move could be stalled by an expensive earlier operation.