forked from OSchip/llvm-project
[X86][SSE] Add tests for 256-bit HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) --> SHUFFLE(HOP(X,Y)) patterns
This should be addressed by combineHorizOpWithShuffle once we enable it for HADD/SUB
This commit is contained in:
Simon Pilgrim
parent
c5683ffeb1
commit
d7d172b4aa
llvm/test/CodeGen/X86
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@ -1116,3 +1116,188 @@ define <4 x i32> @hsub_4i32_v8i32_shuffle(<8 x i32> %a0) {
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%hsub = add <4 x i32> %hsub0, %hsub1
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ret <4 x i32> %hsub
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}
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;
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; fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) --> SHUFFLE(HOP(X,Y)).
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;
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define <4 x double> @hadd_4f64_v4f64_shuffle(<4 x double> %a0, <4 x double> %a1) {
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; SSSE3-LABEL: hadd_4f64_v4f64_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: haddpd %xmm1, %xmm0
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; SSSE3-NEXT: haddpd %xmm3, %xmm2
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; SSSE3-NEXT: movapd %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_4f64_v4f64_shuffle:
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; AVX: # %bb.0:
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX-NEXT: vhaddpd %ymm0, %ymm2, %ymm0
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; AVX-NEXT: retq
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%shuf0 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%shuf1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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%hadd0 = shufflevector <4 x double> %shuf0, <4 x double> %shuf1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%hadd1 = shufflevector <4 x double> %shuf0, <4 x double> %shuf1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%hadd = fadd <4 x double> %hadd0, %hadd1
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ret <4 x double> %hadd
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}
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define <4 x double> @hsub_4f64_v4f64_shuffle(<4 x double> %a0, <4 x double> %a1) {
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; SSSE3-LABEL: hsub_4f64_v4f64_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: hsubpd %xmm1, %xmm0
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; SSSE3-NEXT: hsubpd %xmm3, %xmm2
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; SSSE3-NEXT: movapd %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_4f64_v4f64_shuffle:
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; AVX: # %bb.0:
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX-NEXT: vhsubpd %ymm0, %ymm2, %ymm0
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; AVX-NEXT: retq
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%shuf0 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%shuf1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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%hadd0 = shufflevector <4 x double> %shuf0, <4 x double> %shuf1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%hadd1 = shufflevector <4 x double> %shuf0, <4 x double> %shuf1, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%hadd = fsub <4 x double> %hadd0, %hadd1
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ret <4 x double> %hadd
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}
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define <8 x float> @hadd_8f32_v8f32_shuffle(<8 x float> %a0, <8 x float> %a1) {
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; SSSE3-LABEL: hadd_8f32_v8f32_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: haddps %xmm1, %xmm0
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; SSSE3-NEXT: haddps %xmm3, %xmm2
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; SSSE3-NEXT: movaps %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_8f32_v8f32_shuffle:
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; AVX: # %bb.0:
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX-NEXT: vhaddps %ymm0, %ymm2, %ymm0
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; AVX-NEXT: retq
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%shuf0 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%shuf1 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%hadd0 = shufflevector <8 x float> %shuf0, <8 x float> %shuf1, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%hadd1 = shufflevector <8 x float> %shuf0, <8 x float> %shuf1, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%hadd = fadd <8 x float> %hadd0, %hadd1
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ret <8 x float> %hadd
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}
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define <8 x float> @hsub_8f32_v8f32_shuffle(<8 x float> %a0, <8 x float> %a1) {
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; SSSE3-LABEL: hsub_8f32_v8f32_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: haddps %xmm1, %xmm0
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; SSSE3-NEXT: haddps %xmm3, %xmm2
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; SSSE3-NEXT: movaps %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_8f32_v8f32_shuffle:
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; AVX: # %bb.0:
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX-NEXT: vhaddps %ymm0, %ymm2, %ymm0
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; AVX-NEXT: retq
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%shuf0 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%shuf1 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%hsub0 = shufflevector <8 x float> %shuf0, <8 x float> %shuf1, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%hsub1 = shufflevector <8 x float> %shuf0, <8 x float> %shuf1, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%hsub = fadd <8 x float> %hsub0, %hsub1
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ret <8 x float> %hsub
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}
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define <8 x i32> @hadd_8i32_v8i32_shuffle(<8 x i32> %a0, <8 x i32> %a1) {
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; SSSE3-LABEL: hadd_8i32_v8i32_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: phaddd %xmm1, %xmm0
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; SSSE3-NEXT: phaddd %xmm3, %xmm2
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; SSSE3-NEXT: movdqa %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hadd_8i32_v8i32_shuffle:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vphaddd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vphaddd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hadd_8i32_v8i32_shuffle:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm2
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX2-NEXT: vphaddd %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: retq
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%shuf0 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%shuf1 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%hadd0 = shufflevector <8 x i32> %shuf0, <8 x i32> %shuf1, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%hadd1 = shufflevector <8 x i32> %shuf0, <8 x i32> %shuf1, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%hadd = add <8 x i32> %hadd0, %hadd1
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ret <8 x i32> %hadd
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}
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define <8 x i32> @hsub_8i32_v8i32_shuffle(<8 x i32> %a0, <8 x i32> %a1) {
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; SSSE3-LABEL: hsub_8i32_v8i32_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: phsubd %xmm1, %xmm0
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; SSSE3-NEXT: phsubd %xmm3, %xmm2
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; SSSE3-NEXT: movdqa %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hsub_8i32_v8i32_shuffle:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vphsubd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vphsubd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hsub_8i32_v8i32_shuffle:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm2
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX2-NEXT: vphsubd %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: retq
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%shuf0 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%shuf1 = shufflevector <8 x i32> %a0, <8 x i32> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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%hadd0 = shufflevector <8 x i32> %shuf0, <8 x i32> %shuf1, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%hadd1 = shufflevector <8 x i32> %shuf0, <8 x i32> %shuf1, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%hadd = sub <8 x i32> %hadd0, %hadd1
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ret <8 x i32> %hadd
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}
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define <16 x i16> @hadd_16i16_16i16_shuffle(<16 x i16> %a0, <16 x i16> %a1) {
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; SSSE3-LABEL: hadd_16i16_16i16_shuffle:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: phaddw %xmm1, %xmm0
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; SSSE3-NEXT: phaddw %xmm3, %xmm2
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; SSSE3-NEXT: movdqa %xmm2, %xmm1
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; SSSE3-NEXT: retq
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;
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; AVX1-LABEL: hadd_16i16_16i16_shuffle:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vphaddw %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vphaddw %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: hadd_16i16_16i16_shuffle:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm2
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
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; AVX2-NEXT: vphaddw %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: retq
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%shuf0 = shufflevector <16 x i16> %a0, <16 x i16> %a1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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%shuf1 = shufflevector <16 x i16> %a0, <16 x i16> %a1, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%hadd0 = shufflevector <16 x i16> %shuf0, <16 x i16> %shuf1, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
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%hadd1 = shufflevector <16 x i16> %shuf0, <16 x i16> %shuf1, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
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%hadd = add <16 x i16> %hadd0, %hadd1
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ret <16 x i16> %hadd
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}
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