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Fix more of PR8825 by correctly using rGPR registers when lowering atomic 

compare-and-swap intrinsics.

llvm-svn: 131518
This commit is contained in:
Cameron Zwarich 2011-05-18 02:20:07 +00:00
parent cd482e359e
commit d7c55fe2ef
1 changed files with 11 additions and 2 deletions
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13
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -4860,12 +4860,21 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
unsigned ptr = MI->getOperand(1).getReg(); unsigned ptr = MI->getOperand(1).getReg();
unsigned oldval = MI->getOperand(2).getReg(); unsigned oldval = MI->getOperand(2).getReg();
unsigned newval = MI->getOperand(3).getReg(); unsigned newval = MI->getOperand(3).getReg();
unsigned scratch = BB->getParent()->getRegInfo()
.createVirtualRegister(ARM::GPRRegisterClass);
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc dl = MI->getDebugLoc(); DebugLoc dl = MI->getDebugLoc();
bool isThumb2 = Subtarget->isThumb2(); bool isThumb2 = Subtarget->isThumb2();
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned scratch =
MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass
: ARM::GPRRegisterClass);
if (isThumb2) {
MRI.constrainRegClass(dest, ARM::tGPRRegisterClass);
MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass);
MRI.constrainRegClass(newval, ARM::tGPRRegisterClass);
}
unsigned ldrOpc, strOpc; unsigned ldrOpc, strOpc;
switch (Size) { switch (Size) {
default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); default: llvm_unreachable("unsupported size for AtomicCmpSwap!");