From d7c55fe2ef9557d3fb0fe083ed8453b90b5f4e0d Mon Sep 17 00:00:00 2001 From: Cameron Zwarich Date: Wed, 18 May 2011 02:20:07 +0000 Subject: [PATCH] Fix more of PR8825 by correctly using rGPR registers when lowering atomic compare-and-swap intrinsics. llvm-svn: 131518 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 2b27a7e4e6ab..e3bc3fa9b3da 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4860,12 +4860,21 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, unsigned ptr = MI->getOperand(1).getReg(); unsigned oldval = MI->getOperand(2).getReg(); unsigned newval = MI->getOperand(3).getReg(); - unsigned scratch = BB->getParent()->getRegInfo() - .createVirtualRegister(ARM::GPRRegisterClass); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); bool isThumb2 = Subtarget->isThumb2(); + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + unsigned scratch = + MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass + : ARM::GPRRegisterClass); + + if (isThumb2) { + MRI.constrainRegClass(dest, ARM::tGPRRegisterClass); + MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass); + MRI.constrainRegClass(newval, ARM::tGPRRegisterClass); + } + unsigned ldrOpc, strOpc; switch (Size) { default: llvm_unreachable("unsupported size for AtomicCmpSwap!");