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Rename PrintableName to Name. 

llvm-svn: 47629
This commit is contained in:
Bill Wendling 2008-02-26 21:47:57 +00:00
parent 9eeaae50ca
commit d7a258d325
18 changed files with 52 additions and 53 deletions
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12
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -49,7 +49,7 @@ class Type;
///
struct TargetRegisterDesc {
const char *AsmName; // Assembly language name for the register
const char *PrintableName;// Printable name for the reg (for debugging)
const char *Name; // Printable name for the reg (for debugging)
const unsigned *AliasSet; // Register Alias Set, described above
const unsigned *SubRegs; // Sub-register set, described above
const unsigned *ImmSubRegs; // Immediate sub-register set, described above
@ -376,16 +376,16 @@ public:
return get(RegNo).SuperRegs;
}
/// getAsmName - Return the symbolic target specific name for the
/// getAsmName - Return the symbolic target-specific name for the
/// specified physical register.
const char *getAsmName(unsigned RegNo) const {
return get(RegNo).AsmName;
}
/// getPrintableName - Return the human-readable symbolic target specific name
/// for the specified physical register.
const char *getPrintableName(unsigned RegNo) const {
return get(RegNo).PrintableName;
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
return get(RegNo).Name;
}
/// getNumRegs - Return the number of registers this target has (useful for

2
llvm/lib/CodeGen/LiveInterval.cpp
View File

@ -665,7 +665,7 @@ void LiveRange::dump() const {
void LiveInterval::print(std::ostream &OS,
const TargetRegisterInfo *TRI) const {
if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
OS << TRI->getPrintableName(reg);
OS << TRI->getName(reg);
else
OS << "%reg" << reg;

2
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -189,7 +189,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
void LiveIntervals::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
cerr << tri_->getPrintableName(reg);
cerr << tri_->getName(reg);
else
cerr << "%reg" << reg;
}

2
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -146,7 +146,7 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
const TargetRegisterInfo *TRI = 0) {
if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
if (TRI)
os << " %" << TRI->get(RegNo).PrintableName;
os << " %" << TRI->get(RegNo).Name;
else
os << " %mreg(" << RegNo << ")";
} else

4
llvm/lib/CodeGen/MachineFunction.cpp
View File

@ -214,7 +214,7 @@ void MachineFunction::print(std::ostream &OS) const {
for (MachineRegisterInfo::livein_iterator
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
if (TRI)
OS << " " << TRI->getPrintableName(I->first);
OS << " " << TRI->getName(I->first);
else
OS << " Reg #" << I->first;
@ -228,7 +228,7 @@ void MachineFunction::print(std::ostream &OS) const {
for (MachineRegisterInfo::liveout_iterator
I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
if (TRI)
OS << " " << TRI->getPrintableName(*I);
OS << " " << TRI->getName(*I);
else
OS << " Reg #" << *I;
OS << "\n";

2
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -174,7 +174,7 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
TM = &MF->getTarget();
if (TM)
OS << "%" << TM->getRegisterInfo()->get(getReg()).PrintableName;
OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
else
OS << "%mreg" << getReg();
}

4
llvm/lib/CodeGen/MachineLICM.cpp
View File

@ -251,7 +251,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
*ImpUses; ++ImpUses)
DOUT << " -> " << TRI->getPrintableName(*ImpUses) << "\n";
DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
}
if (I.getDesc().getImplicitDefs()) {
@ -260,7 +260,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
*ImpDefs; ++ImpDefs)
DOUT << " -> " << TRI->getPrintableName(*ImpDefs) << "\n";
DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
}
//if (TII->hasUnmodelledSideEffects(&I))

14
llvm/lib/CodeGen/RegAllocBigBlock.cpp
View File

@ -311,7 +311,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
" the intended one.");
DOUT << " Spilling register " << RegInfo->getPrintableName(PhysReg)
DOUT << " Spilling register " << RegInfo->getName(PhysReg)
<< " containing %reg" << VirtReg;
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@ -535,7 +535,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
markVirtRegModified(VirtReg, false);
DOUT << " Reloading %reg" << VirtReg << " into "
<< RegInfo->getPrintableName(PhysReg) << "\n";
<< RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
@ -646,7 +646,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
DOUT << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
DOUT << "[" << RegInfo->getPrintableName(i)
DOUT << "[" << RegInfo->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
DOUT << "\n");
@ -700,14 +700,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
if (PhysReg) {
DOUT << " Last use of " << RegInfo->getPrintableName(PhysReg)
DOUT << " Last use of " << RegInfo->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Last use of "
<< RegInfo->getPrintableName(*AliasSet)
<< RegInfo->getName(*AliasSet)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(*AliasSet);
}
@ -806,14 +806,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
if (PhysReg) {
DOUT << " Register " << RegInfo->getPrintableName(PhysReg)
DOUT << " Register " << RegInfo->getName(PhysReg)
<< " [%reg" << VirtReg
<< "] is never used, removing it frame live list\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Register " << RegInfo->getPrintableName(*AliasSet)
DOUT << " Register " << RegInfo->getName(*AliasSet)
<< " [%reg" << *AliasSet
<< "] is never used, removing it frame live list\n";
removePhysReg(*AliasSet);

12
llvm/lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -164,7 +164,7 @@ namespace {
if (TargetRegisterInfo::isVirtualRegister(reg)) {
reg = vrm_->getPhys(reg);
}
DOUT << tri_->getPrintableName(reg) << '\n';
DOUT << tri_->getName(reg) << '\n';
}
}
};
@ -239,7 +239,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
// Try to coalesce.
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
DOUT << "Coalescing: " << cur << " -> " << tri_->getPrintableName(SrcReg)
DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg)
<< '\n';
vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, SrcReg);
@ -628,7 +628,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// the free physical register and add this interval to the active
// list.
if (physReg) {
DOUT << tri_->getPrintableName(physReg) << '\n';
DOUT << tri_->getName(physReg) << '\n';
vrm_->assignVirt2Phys(cur->reg, physReg);
prt_->addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin()));
@ -690,7 +690,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
}
DOUT << "\t\tregister with min weight: "
<< tri_->getPrintableName(minReg) << " (" << minWeight << ")\n";
<< tri_->getName(minReg) << " (" << minWeight << ")\n";
// if the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart
@ -869,11 +869,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
if (cur->preference) {
if (prt_->isRegAvail(cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
<< tri_->getPrintableName(cur->preference) << "\n";
<< tri_->getName(cur->preference) << "\n";
return cur->preference;
} else
DOUT << "\t\tunable to assign the preferred register: "
<< tri_->getPrintableName(cur->preference) << "\n";
<< tri_->getName(cur->preference) << "\n";
}
// Scan for the first available register.

16
llvm/lib/CodeGen/RegAllocLocal.cpp
View File

@ -286,7 +286,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
" the intended one.");
DOUT << " Spilling register " << TRI->getPrintableName(PhysReg)
DOUT << " Spilling register " << TRI->getName(PhysReg)
<< " containing %reg" << VirtReg;
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@ -502,7 +502,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
DOUT << " Reloading %reg" << VirtReg << " into "
<< TRI->getPrintableName(PhysReg) << "\n";
<< TRI->getName(PhysReg) << "\n";
// Add move instruction(s)
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
@ -575,7 +575,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
DOUT << " Regs have values: ";
for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
DOUT << "[" << TRI->getPrintableName(i)
DOUT << "[" << TRI->getName(i)
<< ",%reg" << PhysRegsUsed[i] << "] ";
DOUT << "\n");
@ -637,14 +637,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
if (PhysReg) {
DOUT << " Last use of " << TRI->getPrintableName(PhysReg)
DOUT << " Last use of " << TRI->getName(PhysReg)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Last use of "
<< TRI->getPrintableName(*AliasSet)
<< TRI->getName(*AliasSet)
<< "[%reg" << VirtReg <<"], removing it from live set\n";
removePhysReg(*AliasSet);
}
@ -728,7 +728,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
markVirtRegModified(DestVirtReg);
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
DOUT << " Assigning " << TRI->getPrintableName(DestPhysReg)
DOUT << " Assigning " << TRI->getName(DestPhysReg)
<< " to %reg" << DestVirtReg << "\n";
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
}
@ -751,14 +751,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
if (PhysReg) {
DOUT << " Register " << TRI->getPrintableName(PhysReg)
DOUT << " Register " << TRI->getName(PhysReg)
<< " [%reg" << VirtReg
<< "] is never used, removing it frame live list\n";
removePhysReg(PhysReg);
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT << " Register " << TRI->getPrintableName(*AliasSet)
DOUT << " Register " << TRI->getName(*AliasSet)
<< " [%reg" << *AliasSet
<< "] is never used, removing it frame live list\n";
removePhysReg(*AliasSet);

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -4181,8 +4181,7 @@ void SDNode::dump(const SelectionDAG *G) const {
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
if (G && R->getReg() &&
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
cerr << " "
<< G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
cerr << " " << G->getTarget().getRegisterInfo()->getName(R->getReg());
} else {
cerr << " #" << R->getReg();
}

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -134,7 +134,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
if (G && R->getReg() != 0 &&
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
Op = Op + " " +
G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
G->getTarget().getRegisterInfo()->getName(R->getReg());
} else {
Op += " #" + utostr(R->getReg());
}

2
llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -1537,7 +1537,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
cerr << tri_->getPrintableName(reg);
cerr << tri_->getName(reg);
else
cerr << "%reg" << reg;
}

14
llvm/lib/CodeGen/VirtRegMap.cpp
View File

@ -141,7 +141,7 @@ void VirtRegMap::print(std::ostream &OS) const {
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
OS << "[reg" << i << " -> " << TRI->getPrintableName(Virt2PhysMap[i])
OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
<< "]\n";
}
@ -351,7 +351,7 @@ public:
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Remembering SS#" << SlotOrReMat;
DOUT << " in physreg " << TRI->getPrintableName(Reg) << "\n";
DOUT << " in physreg " << TRI->getName(Reg) << "\n";
}
/// canClobberPhysReg - Return true if the spiller is allowed to change the
@ -392,7 +392,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " copied, it is available for use but can no longer be modified\n";
}
}
@ -417,7 +417,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " clobbered, invalidating ";
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
@ -1135,9 +1135,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
else
DOUT << "Reusing SS#" << ReuseSlot;
DOUT << " from physreg "
<< TRI->getPrintableName(PhysReg) << " for vreg"
<< TRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg "
<< TRI->getPrintableName(VRM.getPhys(VirtReg)) << "\n";
<< TRI->getName(VRM.getPhys(VirtReg)) << "\n";
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
@ -1208,7 +1208,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Reusing SS#" << ReuseSlot;
DOUT << " from physreg " << TRI->getPrintableName(PhysReg)
DOUT << " from physreg " << TRI->getName(PhysReg)
<< " for vreg" << VirtReg
<< " instead of reloading into same physreg.\n";
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;

2
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -334,6 +334,6 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
{
std::string s(RegisterDescriptors[reg].PrintableName);
std::string s(RegisterDescriptors[reg].Name);
return s;
}

2
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -25,7 +25,7 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
let PrintableName = n;
let Name = n;
}
// SPR - One of the 32-bit special-purpose registers

2
llvm/lib/Target/Target.td
View File

@ -26,7 +26,7 @@ class RegisterClass; // Forward def
class Register<string n> {
string Namespace = "";
string AsmName = n;
string PrintableName = n;
string Name = n;
// SpillSize - If this value is set to a non-zero value, it is the size in
// bits of the spill slot required to hold this register. If this value is

8
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -525,12 +525,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
else
OS << Reg.getName();
OS << "\",\t\"";
if (!Reg.TheDef->getValueAsString("PrintableName").empty()) {
OS << Reg.TheDef->getValueAsString("PrintableName");
if (!Reg.TheDef->getValueAsString("Name").empty()) {
OS << Reg.TheDef->getValueAsString("Name");
} else {
// Default to "name".
if (!Reg.TheDef->getValueAsString("Name").empty())
OS << Reg.TheDef->getValueAsString("Name");
if (!Reg.TheDef->getValueAsString("AsmName").empty())
OS << Reg.TheDef->getValueAsString("AsmName");
else
OS << Reg.getName();
}