forked from OSchip/llvm-project
[ARM] Split FPExt loads
This extends PerformSplittingToWideningLoad to also handle FP_Ext, as well as sign and zero extends. It uses an integer extending load followed by a VCVTL on the bottom lanes to efficiently perform an fpext on a smaller than legal type. The existing code had to be rewritten a little to not just split the node in two and let legalization handle it from there, but to actually split into legal chunks. Differential Revision: https://reviews.llvm.org/D81340
This commit is contained in:
David Green
parent
06be4bb5e6
commit
d79b57b8bb
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@ -967,6 +967,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::UMIN);
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setTargetDAGCombine(ISD::SMAX);
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setTargetDAGCombine(ISD::UMAX);
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setTargetDAGCombine(ISD::FP_EXTEND);
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}
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if (!Subtarget->hasFP64()) {
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@ -15062,9 +15063,10 @@ static SDValue PerformShiftCombine(SDNode *N,
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return SDValue();
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}
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// Look for a sign/zero extend of a larger than legal load. This can be split
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// into two extending loads, which are simpler to deal with than an arbitrary
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// sign extend.
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// Look for a sign/zero/fpextend extend of a larger than legal load. This can be
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// split into multiple extending loads, which are simpler to deal with than an
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// arbitrary extend. For fp extends we use an integer extending load and a VCVTL
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// to convert the type to an f32.
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static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = N->getOperand(0);
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if (N0.getOpcode() != ISD::LOAD)
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@ -15086,12 +15088,15 @@ static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
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NumElements = 4;
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if (ToEltVT == MVT::i16 && FromEltVT == MVT::i8)
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NumElements = 8;
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if (ToEltVT == MVT::f32 && FromEltVT == MVT::f16)
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NumElements = 4;
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if (NumElements == 0 ||
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FromVT.getVectorNumElements() == NumElements ||
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(FromEltVT != MVT::f16 && FromVT.getVectorNumElements() == NumElements) ||
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FromVT.getVectorNumElements() % NumElements != 0 ||
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!isPowerOf2_32(NumElements))
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return SDValue();
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LLVMContext &C = *DAG.getContext();
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SDLoc DL(LD);
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// Details about the old load
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SDValue Ch = LD->getChain();
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@ -15103,28 +15108,43 @@ static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
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ISD::LoadExtType NewExtType =
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N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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SDValue Offset = DAG.getUNDEF(BasePtr.getValueType());
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EVT NewFromVT = FromVT.getHalfNumVectorElementsVT(*DAG.getContext());
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EVT NewToVT = ToVT.getHalfNumVectorElementsVT(*DAG.getContext());
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unsigned NewOffset = NewFromVT.getSizeInBits() / 8;
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SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
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EVT NewFromVT = EVT::getVectorVT(
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C, EVT::getIntegerVT(C, FromEltVT.getScalarSizeInBits()), NumElements);
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EVT NewToVT = EVT::getVectorVT(
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C, EVT::getIntegerVT(C, ToEltVT.getScalarSizeInBits()), NumElements);
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// Split the load in half, each side of which is extended separately. This
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// is good enough, as legalisation will take it from there. They are either
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// already legal or they will be split further into something that is
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// legal.
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SDValue NewLoad1 = DAG.getLoad(
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ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, BasePtr, Offset,
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LD->getPointerInfo(), NewFromVT, Alignment.value(), MMOFlags, AAInfo);
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SDValue NewLoad2 =
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DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
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LD->getPointerInfo().getWithOffset(NewOffset), NewFromVT,
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Alignment.value(), MMOFlags, AAInfo);
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SmallVector<SDValue, 4> Loads;
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SmallVector<SDValue, 4> Chains;
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for (unsigned i = 0; i < FromVT.getVectorNumElements() / NumElements; i++) {
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unsigned NewOffset = (i * NewFromVT.getSizeInBits()) / 8;
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SDValue NewPtr = DAG.getObjectPtrOffset(DL, BasePtr, NewOffset);
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
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SDValue(NewLoad1.getNode(), 1),
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SDValue(NewLoad2.getNode(), 1));
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SDValue NewLoad =
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DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
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LD->getPointerInfo().getWithOffset(NewOffset), NewFromVT,
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Alignment.value(), MMOFlags, AAInfo);
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Loads.push_back(NewLoad);
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Chains.push_back(SDValue(NewLoad.getNode(), 1));
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}
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// Float truncs need to extended with VCVTB's into their floating point types.
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if (FromEltVT == MVT::f16) {
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SmallVector<SDValue, 4> Extends;
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for (unsigned i = 0; i < Loads.size(); i++) {
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SDValue LoadBC =
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DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v8f16, Loads[i]);
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SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC,
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DAG.getConstant(0, DL, MVT::i32));
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Extends.push_back(FPExt);
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}
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Loads = Extends;
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}
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SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
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DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewChain);
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, NewLoad1, NewLoad2);
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Loads);
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}
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/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
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@ -15172,6 +15192,15 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformFPExtendCombine(SDNode *N, SelectionDAG &DAG,
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const ARMSubtarget *ST) {
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if (ST->hasMVEFloatOps())
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if (SDValue NewLoad = PerformSplittingToWideningLoad(N, DAG))
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return NewLoad;
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return SDValue();
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}
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/// PerformMinMaxCombine - Target-specific DAG combining for creating truncating
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/// saturates.
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static SDValue PerformMinMaxCombine(SDNode *N, SelectionDAG &DAG,
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@ -15830,6 +15859,8 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND:
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return PerformExtendCombine(N, DCI.DAG, Subtarget);
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case ISD::FP_EXTEND:
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return PerformFPExtendCombine(N, DCI.DAG, Subtarget);
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case ISD::SMIN:
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case ISD::UMIN:
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case ISD::SMAX:
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@ -166,18 +166,9 @@ define void @from_4(half* nocapture readonly %x, float* noalias nocapture %y) {
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB3_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr r2, [r0]
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; CHECK-NEXT: ldr r3, [r0, #4]
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; CHECK-NEXT: adds r0, #8
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; CHECK-NEXT: vmov.32 q1[0], r2
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; CHECK-NEXT: vmov.32 q1[1], r3
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; CHECK-NEXT: vmovx.f16 s10, s5
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; CHECK-NEXT: vmovx.f16 s8, s4
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; CHECK-NEXT: vcvtb.f32.f16 s15, s10
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; CHECK-NEXT: vcvtb.f32.f16 s14, s5
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; CHECK-NEXT: vcvtb.f32.f16 s13, s8
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; CHECK-NEXT: vcvtb.f32.f16 s12, s4
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; CHECK-NEXT: vmul.f32 q1, q3, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0], #8
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrb.8 q1, [r1], #16
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; CHECK-NEXT: le lr, .LBB3_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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@ -215,34 +206,22 @@ define void @from_8(half* nocapture readonly %x, float* noalias nocapture %y) {
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: adr r2, .LCPI4_0
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; CHECK-NEXT: mov.w lr, #128
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; CHECK-NEXT: vldrw.u32 q0, [r2]
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB4_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q1, [r0], #16
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; CHECK-NEXT: vmovx.f16 s8, s5
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; CHECK-NEXT: vmovx.f16 s13, s7
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; CHECK-NEXT: vcvtb.f32.f16 s11, s8
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; CHECK-NEXT: vmovx.f16 s14, s6
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; CHECK-NEXT: vcvtb.f32.f16 s10, s5
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; CHECK-NEXT: vcvtb.f32.f16 s19, s13
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; CHECK-NEXT: vcvtb.f32.f16 s18, s7
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; CHECK-NEXT: vmovx.f16 s12, s4
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; CHECK-NEXT: vcvtb.f32.f16 s17, s14
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; CHECK-NEXT: vcvtb.f32.f16 s16, s6
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; CHECK-NEXT: vcvtb.f32.f16 s9, s12
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; CHECK-NEXT: vcvtb.f32.f16 s8, s4
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; CHECK-NEXT: vmul.f32 q1, q4, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1, #16]
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; CHECK-NEXT: vmul.f32 q1, q2, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0], #16
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1], #32
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; CHECK-NEXT: le lr, .LBB4_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.3:
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@ -277,51 +256,30 @@ define void @from_16(half* nocapture readonly %x, float* noalias nocapture %y) {
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: adr r2, .LCPI5_0
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; CHECK-NEXT: mov.w lr, #64
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; CHECK-NEXT: vldrw.u32 q0, [r2]
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB5_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q1, [r0], #32
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; CHECK-NEXT: vmovx.f16 s12, s5
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; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
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; CHECK-NEXT: vcvtb.f32.f16 s15, s12
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; CHECK-NEXT: vmovx.f16 s18, s4
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; CHECK-NEXT: vcvtb.f32.f16 s14, s5
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; CHECK-NEXT: vmovx.f16 s16, s7
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; CHECK-NEXT: vcvtb.f32.f16 s13, s18
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; CHECK-NEXT: vmovx.f16 s20, s9
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; CHECK-NEXT: vcvtb.f32.f16 s12, s4
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; CHECK-NEXT: vcvtb.f32.f16 s19, s16
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; CHECK-NEXT: vmovx.f16 s22, s6
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; CHECK-NEXT: vcvtb.f32.f16 s18, s7
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; CHECK-NEXT: vcvtb.f32.f16 s17, s22
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; CHECK-NEXT: vcvtb.f32.f16 s23, s20
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; CHECK-NEXT: vmovx.f16 s28, s11
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; CHECK-NEXT: vcvtb.f32.f16 s22, s9
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; CHECK-NEXT: vcvtb.f32.f16 s31, s28
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; CHECK-NEXT: vmovx.f16 s26, s10
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; CHECK-NEXT: vcvtb.f32.f16 s30, s11
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; CHECK-NEXT: vmovx.f16 s24, s8
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; CHECK-NEXT: vcvtb.f32.f16 s29, s26
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; CHECK-NEXT: vcvtb.f32.f16 s28, s10
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; CHECK-NEXT: vcvtb.f32.f16 s21, s24
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; CHECK-NEXT: vcvtb.f32.f16 s20, s8
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; CHECK-NEXT: vcvtb.f32.f16 s16, s6
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; CHECK-NEXT: vmul.f32 q1, q7, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0, #24]
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1, #48]
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; CHECK-NEXT: vmul.f32 q1, q5, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0, #16]
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1, #32]
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; CHECK-NEXT: vmul.f32 q1, q4, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1, #16]
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; CHECK-NEXT: vmul.f32 q1, q3, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0], #32
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vstrw.32 q1, [r1], #64
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; CHECK-NEXT: le lr, .LBB5_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.3:
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@ -362,18 +320,9 @@ define void @both_4(half* nocapture readonly %x, half* noalias nocapture %y) {
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB6_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr r2, [r0]
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; CHECK-NEXT: ldr r3, [r0, #4]
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; CHECK-NEXT: adds r0, #8
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; CHECK-NEXT: vmov.32 q1[0], r2
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; CHECK-NEXT: vmov.32 q1[1], r3
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; CHECK-NEXT: vmovx.f16 s10, s5
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; CHECK-NEXT: vmovx.f16 s8, s4
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; CHECK-NEXT: vcvtb.f32.f16 s15, s10
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; CHECK-NEXT: vcvtb.f32.f16 s14, s5
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; CHECK-NEXT: vcvtb.f32.f16 s13, s8
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; CHECK-NEXT: vcvtb.f32.f16 s12, s4
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; CHECK-NEXT: vmul.f32 q1, q3, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0], #8
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vcvtb.f16.f32 q1, q1
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; CHECK-NEXT: vstrh.32 q1, [r1], #8
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; CHECK-NEXT: le lr, .LBB6_1
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@ -419,23 +368,14 @@ define void @both_8(half* nocapture readonly %x, half* noalias nocapture %y) {
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB7_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q1, [r0], #16
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; CHECK-NEXT: vmovx.f16 s10, s7
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; CHECK-NEXT: vmovx.f16 s8, s6
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; CHECK-NEXT: vcvtb.f32.f16 s15, s10
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; CHECK-NEXT: vcvtb.f32.f16 s14, s7
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; CHECK-NEXT: vcvtb.f32.f16 s13, s8
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; CHECK-NEXT: vcvtb.f32.f16 s12, s6
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; CHECK-NEXT: vmul.f32 q2, q3, q0
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; CHECK-NEXT: vcvtb.f16.f32 q2, q2
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; CHECK-NEXT: vstrh.32 q2, [r1, #8]
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; CHECK-NEXT: vmovx.f16 s10, s5
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; CHECK-NEXT: vcvtb.f32.f16 s15, s10
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; CHECK-NEXT: vmovx.f16 s8, s4
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; CHECK-NEXT: vcvtb.f32.f16 s14, s5
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; CHECK-NEXT: vcvtb.f32.f16 s13, s8
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; CHECK-NEXT: vcvtb.f32.f16 s12, s4
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; CHECK-NEXT: vmul.f32 q1, q3, q0
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; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vcvtb.f16.f32 q1, q1
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; CHECK-NEXT: vstrh.32 q1, [r1, #8]
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; CHECK-NEXT: vldrh.u32 q1, [r0], #16
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: vmul.f32 q1, q1, q0
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; CHECK-NEXT: vcvtb.f16.f32 q1, q1
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; CHECK-NEXT: vstrh.32 q1, [r1], #16
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; CHECK-NEXT: le lr, .LBB7_1
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@ -481,42 +421,24 @@ define void @both_16(half* nocapture readonly %x, half* noalias nocapture %y) {
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB8_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q1, [r0, #16]
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; CHECK-NEXT: vmovx.f16 s10, s7
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; CHECK-NEXT: vmovx.f16 s8, s6
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s15, s10
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s14, s7
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s13, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s12, s6
|
||||
; CHECK-NEXT: vmul.f32 q2, q3, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q2, q2
|
||||
; CHECK-NEXT: vstrh.32 q2, [r1, #24]
|
||||
; CHECK-NEXT: vmovx.f16 s10, s5
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s15, s10
|
||||
; CHECK-NEXT: vmovx.f16 s8, s4
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s14, s5
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s13, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s12, s4
|
||||
; CHECK-NEXT: vmul.f32 q1, q3, q0
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0, #24]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: vmul.f32 q1, q1, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
|
||||
; CHECK-NEXT: vstrh.32 q1, [r1, #24]
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: vmul.f32 q1, q1, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
|
||||
; CHECK-NEXT: vstrh.32 q1, [r1, #16]
|
||||
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
|
||||
; CHECK-NEXT: vmovx.f16 s10, s7
|
||||
; CHECK-NEXT: vmovx.f16 s8, s6
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s15, s10
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s14, s7
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s13, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s12, s6
|
||||
; CHECK-NEXT: vmul.f32 q2, q3, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q2, q2
|
||||
; CHECK-NEXT: vstrh.32 q2, [r1, #8]
|
||||
; CHECK-NEXT: vmovx.f16 s10, s5
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s15, s10
|
||||
; CHECK-NEXT: vmovx.f16 s8, s4
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s14, s5
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s13, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s12, s4
|
||||
; CHECK-NEXT: vmul.f32 q1, q3, q0
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: vmul.f32 q1, q1, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
|
||||
; CHECK-NEXT: vstrh.32 q1, [r1, #8]
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0], #32
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: vmul.f32 q1, q1, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 q1, q1
|
||||
; CHECK-NEXT: vstrh.32 q1, [r1], #32
|
||||
; CHECK-NEXT: le lr, .LBB8_1
|
||||
|
|
|
|||
|
|
@ -217,15 +217,8 @@ entry:
|
|||
define arm_aapcs_vfpcc <4 x float> @load_ext_4(<4 x half>* %src) {
|
||||
; CHECK-LABEL: load_ext_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: ldrd r1, r0, [r0]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r1
|
||||
; CHECK-NEXT: vmov.32 q1[1], r0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s5
|
||||
; CHECK-NEXT: vmovx.f16 s8, s4
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s2, s5
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s1, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s4
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%wide.load = load <4 x half>, <4 x half>* %src, align 4
|
||||
|
|
@ -236,19 +229,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x float> @load_ext_8(<8 x half>* %src) {
|
||||
; CHECK-LABEL: load_ext_8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vmovx.f16 s0, s9
|
||||
; CHECK-NEXT: vmovx.f16 s6, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
|
||||
; CHECK-NEXT: vmovx.f16 s4, s11
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s2, s9
|
||||
; CHECK-NEXT: vmovx.f16 s12, s10
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s1, s6
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s7, s4
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s6, s11
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s5, s12
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s4, s10
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q0, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%wide.load = load <8 x half>, <8 x half>* %src, align 4
|
||||
|
|
@ -259,35 +243,14 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x float> @load_ext_16(<16 x half>* %src) {
|
||||
; CHECK-LABEL: load_ext_16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10}
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
|
||||
; CHECK-NEXT: vmovx.f16 s0, s9
|
||||
; CHECK-NEXT: vmovx.f16 s6, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s3, s0
|
||||
; CHECK-NEXT: vmovx.f16 s4, s11
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s2, s9
|
||||
; CHECK-NEXT: vmovx.f16 s15, s10
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s1, s6
|
||||
; CHECK-NEXT: vmovx.f16 s13, s17
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s8
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s7, s4
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s6, s11
|
||||
; CHECK-NEXT: vmovx.f16 s14, s16
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s5, s15
|
||||
; CHECK-NEXT: vmovx.f16 s12, s19
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s4, s10
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s11, s13
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s10, s17
|
||||
; CHECK-NEXT: vmovx.f16 s20, s18
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s9, s14
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s8, s16
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s15, s12
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s14, s19
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s13, s20
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s12, s18
|
||||
; CHECK-NEXT: vpop {d8, d9, d10}
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
|
||||
; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
|
||||
; CHECK-NEXT: vldrh.u32 q3, [r0, #24]
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q0, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q1, q1
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q2, q2
|
||||
; CHECK-NEXT: vcvtb.f32.f16 q3, q3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%wide.load = load <16 x half>, <16 x half>* %src, align 4
|
||||
|
|
|
|||
|
|
@ -134,14 +134,14 @@ entry:
|
|||
define void @foo_int32_int8_double(<16 x i32>* %dest, <16 x i8>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_int32_int8_double:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1, #4]
|
||||
; CHECK-NEXT: vldrb.s32 q1, [r1]
|
||||
; CHECK-NEXT: vldrb.s32 q2, [r1, #12]
|
||||
; CHECK-NEXT: vldrb.s32 q3, [r1, #8]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #32]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #48]
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r1]
|
||||
; CHECK-NEXT: vldrb.s32 q1, [r1, #4]
|
||||
; CHECK-NEXT: vldrb.s32 q2, [r1, #8]
|
||||
; CHECK-NEXT: vldrb.s32 q3, [r1, #12]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #48]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #32]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%wide.load = load <16 x i8>, <16 x i8>* %src, align 1
|
||||
|
|
@ -224,14 +224,14 @@ entry:
|
|||
define void @foo_uint32_uint8_double(<16 x i32>* %dest, <16 x i8>* readonly %src, i32 %n) {
|
||||
; CHECK-LABEL: foo_uint32_uint8_double:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1, #4]
|
||||
; CHECK-NEXT: vldrb.u32 q1, [r1]
|
||||
; CHECK-NEXT: vldrb.u32 q2, [r1, #12]
|
||||
; CHECK-NEXT: vldrb.u32 q3, [r1, #8]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #32]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #48]
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vldrb.u32 q1, [r1, #4]
|
||||
; CHECK-NEXT: vldrb.u32 q2, [r1, #8]
|
||||
; CHECK-NEXT: vldrb.u32 q3, [r1, #12]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #48]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #32]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%wide.load = load <16 x i8>, <16 x i8>* %src, align 1
|
||||
|
|
@ -347,12 +347,12 @@ define <16 x i16>* @foo_uint32_uint16_quad_offset(<16 x i32>* %dest, <16 x i16>*
|
|||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r1, #32]!
|
||||
; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
|
||||
; CHECK-NEXT: vldrh.s32 q2, [r1, #24]
|
||||
; CHECK-NEXT: vldrh.s32 q3, [r1, #16]
|
||||
; CHECK-NEXT: vldrh.s32 q2, [r1, #16]
|
||||
; CHECK-NEXT: vldrh.s32 q3, [r1, #24]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #48]
|
||||
; CHECK-NEXT: vstrw.32 q2, [r0, #32]
|
||||
; CHECK-NEXT: vstrw.32 q1, [r0, #16]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #32]
|
||||
; CHECK-NEXT: vstrw.32 q3, [r0, #48]
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
|
|||
Loading…
Reference in New Issue