forked from OSchip/llvm-project
AMDGPU: Use GOT PSV since it has an address space now
llvm-svn: 341768
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@ -4447,8 +4447,8 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
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PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
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const DataLayout &DataLayout = DAG.getDataLayout();
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unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
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// FIXME: Use a PseudoSourceValue once those can be assigned an address space.
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MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
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MachinePointerInfo PtrInfo
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= MachinePointerInfo::getGOT(DAG.getMachineFunction());
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return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
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MachineMemOperand::MODereferenceable |
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@ -1,4 +1,4 @@
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; RUN: llc -O2 -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads=true -verify-machineinstrs < %s | FileCheck %s
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; uniform loads
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; CHECK-LABEL: @uniform_load
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@ -81,10 +81,10 @@ define amdgpu_kernel void @memdep(i32 addrspace(1)* %in, [8 x i32], i32 addrspac
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; uniform load from global array
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; CHECK-LABEL: @global_array
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; CHECK: s_getpc_b64 [[GET_PC:s\[[0-9]+:[0-9]+\]]]
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; CHECK: s_load_dwordx2 [[OUT:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0
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; CHECK: s_load_dwordx2 [[A_ADDR:s\[[0-9]+:[0-9]+\]]], [[GET_PC]], 0x0
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; CHECK: s_load_dwordx2 [[A_ADDR1:s\[[0-9]+:[0-9]+\]]], [[A_ADDR]], 0x0
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; CHECK: s_load_dword [[SVAL:s[0-9]+]], [[A_ADDR1]], 0x0
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; CHECK: s_load_dwordx2 [[OUT:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[SVAL]]
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; CHECK: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[VVAL]]
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@A = common local_unnamed_addr addrspace(1) global i32 addrspace(1)* null, align 4
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