forked from OSchip/llvm-project
[Hexagon] Implement HexagonSubtarget::useAA()
llvm-svn: 319477
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@ -92,7 +92,7 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
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HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
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StringRef FS, const TargetMachine &TM)
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: HexagonGenSubtargetInfo(TT, CPU, FS),
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: HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
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CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)),
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RegInfo(getHwMode()), TLInfo(TM, *this),
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@ -294,6 +294,14 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
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}
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}
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/// \brief Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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bool HexagonSubtarget::useAA() const {
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if (OptLevel != CodeGenOpt::None)
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return true;
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return false;
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}
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/// \brief Perform target specific adjustments to the latency of a schedule
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/// dependency.
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void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
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@ -53,6 +53,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
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public:
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Hexagon::ArchEnum HexagonArchVersion;
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Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4;
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CodeGenOpt::Level OptLevel;
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/// True if the target should use Back-Skip-Back scheduling. This is the
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/// default for V60.
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bool UseBSBScheduling;
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@ -177,6 +178,10 @@ public:
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std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
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const override;
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/// \brief Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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bool useAA() const override;
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/// \brief Perform target specific adjustments to the latency of a schedule
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/// dependency.
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void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
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