forked from OSchip/llvm-project
[msan] Heuristically instrument unknown intrinsics.
This changes adds shadow and origin propagation for unknown intrinsics by examining the arguments and ModRef behaviour. For now, only 3 classes of intrinsics are handled: - those that look like simple SIMD store - those that look like simple SIMD load - those that don't have memory effects and look like arithmetic/logic/whatever operation on simple types. llvm-svn: 170530
This commit is contained in:
Evgeniy Stepanov
parent
fd41b5b969
commit
d7571cd4bc
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@ -1210,6 +1210,147 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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VAHelper->visitVACopyInst(I);
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}
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enum IntrinsicKind {
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IK_DoesNotAccessMemory,
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IK_OnlyReadsMemory,
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IK_WritesMemory
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};
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static IntrinsicKind getIntrinsicKind(Intrinsic::ID iid) {
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const int DoesNotAccessMemory = IK_DoesNotAccessMemory;
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const int OnlyReadsArgumentPointees = IK_OnlyReadsMemory;
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const int OnlyReadsMemory = IK_OnlyReadsMemory;
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const int OnlyAccessesArgumentPointees = IK_WritesMemory;
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const int UnknownModRefBehavior = IK_WritesMemory;
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#define GET_INTRINSIC_MODREF_BEHAVIOR
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#define ModRefBehavior IntrinsicKind
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#include "llvm/Intrinsics.gen"
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#undef ModRefBehavior
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#undef GET_INTRINSIC_MODREF_BEHAVIOR
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}
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/// \brief Handle vector store-like intrinsics.
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///
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/// Instrument intrinsics that look like a simple SIMD store: writes memory,
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/// has 1 pointer argument and 1 vector argument, returns void.
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bool handleVectorStoreIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value* Addr = I.getArgOperand(0);
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Value *Shadow = getShadow(&I, 1);
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Value *ShadowPtr = getShadowPtr(Addr, Shadow->getType(), IRB);
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// We don't know the pointer alignment (could be unaligned SSE store!).
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// Have to assume to worst case.
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IRB.CreateAlignedStore(Shadow, ShadowPtr, 1);
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if (ClCheckAccessAddress)
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insertCheck(Addr, &I);
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// FIXME: use ClStoreCleanOrigin
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// FIXME: factor out common code from materializeStores
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if (ClTrackOrigins)
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IRB.CreateStore(getOrigin(&I, 1), getOriginPtr(Addr, IRB));
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return true;
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}
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/// \brief Handle vector load-like intrinsics.
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///
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/// Instrument intrinsics that look like a simple SIMD load: reads memory,
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/// has 1 pointer argument, returns a vector.
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bool handleVectorLoadIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *Addr = I.getArgOperand(0);
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Type *ShadowTy = getShadowTy(&I);
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Value *ShadowPtr = getShadowPtr(Addr, ShadowTy, IRB);
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// We don't know the pointer alignment (could be unaligned SSE load!).
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// Have to assume to worst case.
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setShadow(&I, IRB.CreateAlignedLoad(ShadowPtr, 1, "_msld"));
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if (ClCheckAccessAddress)
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insertCheck(Addr, &I);
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if (ClTrackOrigins)
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setOrigin(&I, IRB.CreateLoad(getOriginPtr(Addr, IRB)));
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return true;
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}
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/// \brief Handle (SIMD arithmetic)-like intrinsics.
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///
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/// Instrument intrinsics with any number of arguments of the same type,
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/// equal to the return type. The type should be simple (no aggregates or
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/// pointers; vectors are fine).
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/// Caller guarantees that this intrinsic does not access memory.
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bool maybeHandleSimpleNomemIntrinsic(IntrinsicInst &I) {
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Type *RetTy = I.getType();
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if (!(RetTy->isIntOrIntVectorTy() ||
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RetTy->isFPOrFPVectorTy() ||
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RetTy->isX86_MMXTy()))
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return false;
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unsigned NumArgOperands = I.getNumArgOperands();
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for (unsigned i = 0; i < NumArgOperands; ++i) {
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Type *Ty = I.getArgOperand(i)->getType();
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if (Ty != RetTy)
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return false;
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}
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IRBuilder<> IRB(&I);
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ShadowAndOriginCombiner SC(this, IRB);
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for (unsigned i = 0; i < NumArgOperands; ++i)
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SC.Add(I.getArgOperand(i));
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SC.Done(&I);
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return true;
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}
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/// \brief Heuristically instrument unknown intrinsics.
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///
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/// The main purpose of this code is to do something reasonable with all
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/// random intrinsics we might encounter, most importantly - SIMD intrinsics.
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/// We recognize several classes of intrinsics by their argument types and
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/// ModRefBehaviour and apply special intrumentation when we are reasonably
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/// sure that we know what the intrinsic does.
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///
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/// We special-case intrinsics where this approach fails. See llvm.bswap
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/// handling as an example of that.
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bool handleUnknownIntrinsic(IntrinsicInst &I) {
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unsigned NumArgOperands = I.getNumArgOperands();
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if (NumArgOperands == 0)
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return false;
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Intrinsic::ID iid = I.getIntrinsicID();
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IntrinsicKind IK = getIntrinsicKind(iid);
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bool OnlyReadsMemory = IK == IK_OnlyReadsMemory;
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bool WritesMemory = IK == IK_WritesMemory;
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assert(!(OnlyReadsMemory && WritesMemory));
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if (NumArgOperands == 2 &&
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I.getArgOperand(0)->getType()->isPointerTy() &&
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I.getArgOperand(1)->getType()->isVectorTy() &&
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I.getType()->isVoidTy() &&
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WritesMemory) {
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// This looks like a vector store.
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return handleVectorStoreIntrinsic(I);
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}
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if (NumArgOperands == 1 &&
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I.getArgOperand(0)->getType()->isPointerTy() &&
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I.getType()->isVectorTy() &&
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OnlyReadsMemory) {
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// This looks like a vector load.
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return handleVectorLoadIntrinsic(I);
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}
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if (!OnlyReadsMemory && !WritesMemory)
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if (maybeHandleSimpleNomemIntrinsic(I))
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return true;
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// FIXME: detect and handle SSE maskstore/maskload
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return false;
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}
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void handleBswap(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Value *Op = I.getArgOperand(0);
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@ -1226,6 +1367,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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handleBswap(I);
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break;
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default:
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if (!handleUnknownIntrinsic(I))
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visitInstruction(I);
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break;
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}
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@ -1,5 +1,5 @@
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; RUN: opt < %s -msan -S | FileCheck %s
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; RUN: opt < %s -msan -msan-track-origins=1 -S | FileCheck -check-prefix=CHECK-ORIGINS %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck -check-prefix=CHECK-ORIGINS %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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; Check the presence of __msan_init
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@ -408,6 +408,7 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) {
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; CHECK: shufflevector
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; CHECK: ret <4 x i32>
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; Test bswap intrinsic instrumentation
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define i32 @BSwap(i32 %x) nounwind uwtable readnone {
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%y = tail call i32 @llvm.bswap.i32(i32 %x)
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@ -423,3 +424,74 @@ declare i32 @llvm.bswap.i32(i32) nounwind readnone
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; CHECK: @llvm.bswap.i32
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; CHECK-NOT: call void @__msan_warning
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; CHECK: ret i32
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; Store intrinsic.
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define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable {
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call void @llvm.x86.sse.storeu.ps(i8* %p, <4 x float> %x)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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; CHECK: @StoreIntrinsic
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; CHECK-NOT: br
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; CHECK-NOT: = or
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; CHECK: store <4 x i32> {{.*}} align 1
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; CHECK: call void @llvm.x86.sse.storeu.ps
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; CHECK: ret void
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; Load intrinsic.
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define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable {
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%call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p)
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ret <16 x i8> %call
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}
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declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
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; CHECK: @LoadIntrinsic
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; CHECK: load <16 x i8>* {{.*}} align 1
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; CHECK-NOT: br
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; CHECK-NOT: = or
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; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
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; CHECK: store <16 x i8> {{.*}} @__msan_retval_tls
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; CHECK: ret <16 x i8>
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; CHECK-ORIGINS: @LoadIntrinsic
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; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32* {{.*}}
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; CHECK-ORIGINS: call <16 x i8> @llvm.x86.sse3.ldu.dq
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; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], i32* @__msan_retval_origin_tls
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; CHECK-ORIGINS: ret <16 x i8>
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; Simple NoMem intrinsic
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; Check that shadow is OR'ed, and origin is Select'ed
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; And no shadow checks!
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define <8 x i16> @Paddsw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable {
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%call = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %a, <8 x i16> %b) nounwind
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; CHECK: @Paddsw128
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; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
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; CHECK-NEXT: load <8 x i16>* {{.*}} @__msan_param_tls
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; CHECK-NEXT: = or <8 x i16>
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; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.padds.w
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; CHECK-NEXT: store <8 x i16> {{.*}} @__msan_retval_tls
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; CHECK-NEXT: ret <8 x i16>
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; CHECK-ORIGINS: @Paddsw128
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; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
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; CHECK-ORIGINS: load i32* {{.*}} @__msan_param_origin_tls
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; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128
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; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0
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; CHECK-ORIGINS-NEXT: = select i1 {{.*}}, i32 {{.*}}, i32
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; CHECK-ORIGINS: call <8 x i16> @llvm.x86.sse2.padds.w
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; CHECK-ORIGINS: store i32 {{.*}} @__msan_retval_origin_tls
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; CHECK-ORIGINS: ret <8 x i16>
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