forked from OSchip/llvm-project
Adapt the code for handling uint -> fp conversion for the 32 bit case to
handling it in the 64 bit case. The two code paths should probably be merged. llvm-svn: 22302
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@ -1314,6 +1314,41 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::UINT_TO_FP:
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Legal:
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//still made need to expand if the op is illegal, but the types are legal
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if (Node->getOpcode() == ISD::UINT_TO_FP &&
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TLI.getOperationAction(Node->getOpcode(),
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Node->getOperand(0).getValueType())
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== TargetLowering::Expand) {
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Tmp1 = DAG.getNode(ISD::SINT_TO_FP, Node->getValueType(0),
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Node->getOperand(0));
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SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(),
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Node->getOperand(0),
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DAG.getConstant(0,
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Node->getOperand(0).getValueType()));
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SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
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SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
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SignSet, Four, Zero);
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uint64_t FF = 0x5f800000ULL;
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if (TLI.isLittleEndian()) FF <<= 32;
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static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
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MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
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SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor),
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TLI.getPointerTy());
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CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
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SDOperand FudgeInReg;
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if (Node->getValueType(0) == MVT::f32)
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FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
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DAG.getSrcValue(NULL));
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else {
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assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
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FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
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CPIdx, DAG.getSrcValue(NULL), MVT::f32);
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}
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Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
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break;
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}
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Tmp1 = LegalizeOp(Node->getOperand(0));
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if (Tmp1 != Node->getOperand(0))
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
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