forked from OSchip/llvm-project
[SimplifyCFG] SimplifyCondBranchToTwoReturns(): really only deal with different ret blocks
This function is called when some predecessor of an empty return block ends with a conditional branch, with both successors being empty ret blocks. Now, because of the way SimplifyCFG works, it might happen to simplify one of the blocks in a way that makes a conditional branch into an unconditional one, since it's destinations are now identical, but it might not have actually simplified said conditional branch into an unconditional one yet. So, we have to check that ourselves first, especially now that SimplifyCFG aggressively tail-merges all ret and resume blocks. Even if it was an unconditional branch already, `SimplifyCFGOpt::simplifyReturn()` doesn't call `FoldReturnIntoUncondBranch()` by default.
This commit is contained in:
Roman Lebedev
parent
0d4f2de303
commit
d7378259aa
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@ -2891,6 +2891,8 @@ bool SimplifyCFGOpt::SimplifyCondBranchToTwoReturns(BranchInst *BI,
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assert(BI->isConditional() && "Must be a conditional branch");
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BasicBlock *TrueSucc = BI->getSuccessor(0);
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BasicBlock *FalseSucc = BI->getSuccessor(1);
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if (TrueSucc == FalseSucc)
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return false;
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// NOTE: destinations may match, this could be degenerate uncond branch.
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ReturnInst *TrueRet = cast<ReturnInst>(TrueSucc->getTerminator());
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ReturnInst *FalseRet = cast<ReturnInst>(FalseSucc->getTerminator());
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@ -2912,13 +2914,9 @@ bool SimplifyCFGOpt::SimplifyCondBranchToTwoReturns(BranchInst *BI,
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FalseSucc->removePredecessor(BB);
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Builder.CreateRetVoid();
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EraseTerminatorAndDCECond(BI);
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if (DTU) {
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SmallVector<DominatorTree::UpdateType, 2> Updates;
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Updates.push_back({DominatorTree::Delete, BB, TrueSucc});
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if (TrueSucc != FalseSucc)
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Updates.push_back({DominatorTree::Delete, BB, FalseSucc});
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DTU->applyUpdates(Updates);
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}
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if (DTU)
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DTU->applyUpdates({{DominatorTree::Delete, BB, TrueSucc},
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{DominatorTree::Delete, BB, FalseSucc}});
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return true;
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}
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@ -2975,13 +2973,9 @@ bool SimplifyCFGOpt::SimplifyCondBranchToTwoReturns(BranchInst *BI,
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<< *TrueSucc << "\nFALSEBLOCK: " << *FalseSucc);
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EraseTerminatorAndDCECond(BI);
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if (DTU) {
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SmallVector<DominatorTree::UpdateType, 2> Updates;
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Updates.push_back({DominatorTree::Delete, BB, TrueSucc});
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if (TrueSucc != FalseSucc)
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Updates.push_back({DominatorTree::Delete, BB, FalseSucc});
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DTU->applyUpdates(Updates);
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}
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if (DTU)
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DTU->applyUpdates({{DominatorTree::Delete, BB, TrueSucc},
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{DominatorTree::Delete, BB, FalseSucc}});
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return true;
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}
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@ -10,6 +10,7 @@ target datalayout = "e-p:64:64:64"
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define i32 @pmat(i32 %m, i32 %n, double* %y) nounwind {
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; CHECK-LABEL: @pmat(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[M:%.*]], 0
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; CHECK-NEXT: ret i32 0
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;
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entry:
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@ -2594,7 +2594,7 @@ define void @test_chr_with_bbs_address_taken2(i32* %i) !prof !14 {
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; CHECK: bb0:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK-NEXT: br label [[BB6:%.*]]
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; CHECK: entry.split.nonchr:
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1
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; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
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@ -2605,11 +2605,11 @@ define void @test_chr_with_bbs_address_taken2(i32* %i) !prof !14 {
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; CHECK: bb1.nonchr:
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; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
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; CHECK-NEXT: br i1 [[TMP5]], label [[BB6]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
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; CHECK: bb2.nonchr:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: br label [[BB6]]
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; CHECK: bb6:
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; CHECK-NEXT: ret void
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;
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entry:
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@ -11,10 +11,7 @@ define float @test_merge_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[LOR_LHS_FALSE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret float [[COMMON_RET_OP]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: lor.lhs.false:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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@ -23,8 +20,11 @@ define float @test_merge_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[LOR_LHS_FALSE]] ]
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; CHECK-NEXT: ret float [[RETVAL_0]]
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;
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entry:
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%vecext = extractelement <4 x float> %t, i32 0
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@ -180,10 +180,7 @@ define float @test_separate_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret float [[COMMON_RET_OP]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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@ -192,8 +189,11 @@ define float @test_separate_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ]
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; CHECK-NEXT: ret float [[RETVAL_0]]
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;
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entry:
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%vecext = extractelement <4 x float> %t, i32 0
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@ -513,10 +513,7 @@ define i32 @test_separate_allof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR6]], <i32 255, i32 255, i32 255, i32 255>
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@ -525,8 +522,11 @@ define i32 @test_separate_allof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], i32 0, i32 [[ADD]]
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], i32 0, i32 [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ]
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; CHECK-NEXT: ret i32 [[RETVAL_0]]
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;
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entry:
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%vecext = extractelement <4 x i32> %t, i32 0
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@ -592,10 +592,7 @@ define i32 @test_separate_anyof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
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; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[COMMON_RET:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
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; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR6]], <i32 255, i32 255, i32 255, i32 255>
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@ -604,8 +601,11 @@ define i32 @test_separate_anyof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[DOTNOT7]], i32 [[ADD]], i32 0
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT7]], i32 [[ADD]], i32 0
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[IF_END]] ]
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; CHECK-NEXT: ret i32 [[RETVAL_0]]
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;
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entry:
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%vecext = extractelement <4 x i32> %t, i32 0
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@ -292,15 +292,15 @@ define i1 @cmp_lt_gt(double %a, double %b, double %c) {
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; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[DIV]], 0x3EB0C6F7A0B5ED8D
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; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[DIV3]], 0x3EB0C6F7A0B5ED8D
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; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
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; CHECK-NEXT: br i1 [[OR_COND]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[OR_COND1:%.*]], [[LOR_LHS_FALSE]] ], [ false, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: lor.lhs.false:
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; CHECK-NEXT: [[CMP5:%.*]] = fcmp ule double [[DIV]], 1.000000e+00
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; CHECK-NEXT: [[CMP7:%.*]] = fcmp ule double [[DIV3]], 1.000000e+00
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; CHECK-NEXT: [[OR_COND1]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]]
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]]
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; CHECK-NEXT: br label [[CLEANUP]]
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; CHECK: cleanup:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[OR_COND1]], [[LOR_LHS_FALSE]] ]
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; CHECK-NEXT: ret i1 [[RETVAL_0]]
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;
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entry:
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%fneg = fneg double %b
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@ -51,9 +51,10 @@ define i32* @can_trap2() {
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TOBOOL]], label [[EXIT:%.*]], label [[BLOCK1:%.*]]
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; CHECK: block1:
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; CHECK-NEXT: ret i32* null
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32* select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a)
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32* [ select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), [[ENTRY:%.*]] ], [ null, [[BLOCK1]] ]
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; CHECK-NEXT: ret i32* [[STOREMERGE]]
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;
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entry:
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%0 = load i32, i32* @a, align 4
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@ -76,12 +77,9 @@ define i32* @cannot_trap() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0
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; CHECK-NEXT: br i1 [[TOBOOL]], label [[EXIT:%.*]], label [[BLOCK1:%.*]]
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; CHECK: block1:
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), i32* select (i1 icmp eq (i64 add (i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64), i64 2), i64 0), i32* null, i32* @a), i32* null
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; CHECK-NEXT: ret i32* [[SPEC_SELECT]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32* null
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; CHECK-NEXT: [[STOREMERGE:%.*]] = select i1 [[TOBOOL]], i32* null, i32* [[SPEC_SELECT]]
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; CHECK-NEXT: ret i32* [[STOREMERGE]]
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;
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entry:
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%0 = load i32, i32* @a, align 4
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@ -123,14 +123,11 @@ define i32* @test5(i32 %a, i32 %b, i32 %c, i32* dereferenceable(10) %ptr1, i32*
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0
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; CHECK-NEXT: br i1 [[T1]], label [[BB1:%.*]], label [[BB3:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 1
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; CHECK-NEXT: [[T3:%.*]] = load i32*, i32** [[PTR3:%.*]], align 8
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[T2]], i32* [[T3]], i32* [[PTR2:%.*]]
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; CHECK-NEXT: ret i32* [[SPEC_SELECT]]
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; CHECK: bb3:
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; CHECK-NEXT: ret i32* [[PTR1:%.*]]
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; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32* [[SPEC_SELECT]], i32* [[PTR1:%.*]]
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; CHECK-NEXT: ret i32* [[T4]]
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;
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entry:
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%t1 = icmp eq i32 %b, 0
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@ -40,9 +40,10 @@ define i1 @PR32078(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[EXIT:%.*]], label [[CMP1_TRUE:%.*]]
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; CHECK: cmp1_true:
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP2]], i1 [[CMP3]], i1 false
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; CHECK-NEXT: ret i1 [[SPEC_SELECT]]
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret i1 false
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; CHECK-NEXT: [[R:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[CMP1_TRUE]] ]
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; CHECK-NEXT: ret i1 [[R]]
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;
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entry:
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%cmp = icmp eq <4 x i32> %a, %b
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@ -52,13 +52,16 @@ define i32 @test3(i1 %C0, i1 %C1, i32 %v0, i32 %v1, i32 %v2) {
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; NODUPRET-NEXT: entry:
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; NODUPRET-NEXT: call void @sideeffect0()
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; NODUPRET-NEXT: br i1 [[C0:%.*]], label [[T:%.*]], label [[F:%.*]]
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; NODUPRET: end:
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; NODUPRET-NEXT: [[R:%.*]] = phi i32 [ [[V2:%.*]], [[F]] ], [ [[SPEC_SELECT:%.*]], [[T]] ]
|
||||
; NODUPRET-NEXT: ret i32 [[R]]
|
||||
; NODUPRET: T:
|
||||
; NODUPRET-NEXT: call void @sideeffect1()
|
||||
; NODUPRET-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[C1:%.*]], i32 [[V0:%.*]], i32 [[V1:%.*]]
|
||||
; NODUPRET-NEXT: ret i32 [[SPEC_SELECT]]
|
||||
; NODUPRET-NEXT: [[SPEC_SELECT]] = select i1 [[C1:%.*]], i32 [[V0:%.*]], i32 [[V1:%.*]]
|
||||
; NODUPRET-NEXT: br label [[END:%.*]]
|
||||
; NODUPRET: F:
|
||||
; NODUPRET-NEXT: call void @sideeffect2()
|
||||
; NODUPRET-NEXT: ret i32 [[V2:%.*]]
|
||||
; NODUPRET-NEXT: br label [[END]]
|
||||
;
|
||||
; DUPRET-LABEL: @test3(
|
||||
; DUPRET-NEXT: entry:
|
||||
|
|
@ -76,14 +79,17 @@ define i32 @test3(i1 %C0, i1 %C1, i32 %v0, i32 %v1, i32 %v2) {
|
|||
; DBGINFO-NEXT: entry:
|
||||
; DBGINFO-NEXT: call void @sideeffect0(), !dbg [[DBG21:![0-9]+]]
|
||||
; DBGINFO-NEXT: br i1 [[C0:%.*]], label [[T:%.*]], label [[F:%.*]], !dbg [[DBG22:![0-9]+]]
|
||||
; DBGINFO: end:
|
||||
; DBGINFO-NEXT: [[R:%.*]] = phi i32 [ [[V2:%.*]], [[F]] ], [ [[SPEC_SELECT:%.*]], [[T]] ], !dbg [[DBG23:![0-9]+]]
|
||||
; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[R]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23]]
|
||||
; DBGINFO-NEXT: ret i32 [[R]], !dbg [[DBG24:![0-9]+]]
|
||||
; DBGINFO: T:
|
||||
; DBGINFO-NEXT: call void @sideeffect1(), !dbg [[DBG23:![0-9]+]]
|
||||
; DBGINFO-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[C1:%.*]], i32 [[V0:%.*]], i32 [[V1:%.*]], !dbg [[DBG24:![0-9]+]]
|
||||
; DBGINFO-NEXT: ret i32 [[SPEC_SELECT]], !dbg [[DBG24]]
|
||||
; DBGINFO-NEXT: call void @sideeffect1(), !dbg [[DBG25:![0-9]+]]
|
||||
; DBGINFO-NEXT: [[SPEC_SELECT]] = select i1 [[C1:%.*]], i32 [[V0:%.*]], i32 [[V1:%.*]], !dbg [[DBG26:![0-9]+]]
|
||||
; DBGINFO-NEXT: br label [[END:%.*]], !dbg [[DBG26]]
|
||||
; DBGINFO: F:
|
||||
; DBGINFO-NEXT: call void @sideeffect2(), !dbg [[DBG25:![0-9]+]]
|
||||
; DBGINFO-NEXT: call void @llvm.dbg.value(metadata i32 [[V2:%.*]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26:![0-9]+]]
|
||||
; DBGINFO-NEXT: ret i32 [[V2]], !dbg [[DBG27:![0-9]+]]
|
||||
; DBGINFO-NEXT: call void @sideeffect2(), !dbg [[DBG27:![0-9]+]]
|
||||
; DBGINFO-NEXT: br label [[END]], !dbg [[DBG28:![0-9]+]]
|
||||
;
|
||||
entry:
|
||||
call void @sideeffect0()
|
||||
|
|
|
|||
Loading…
Reference in New Issue