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[Hexagon] Make getHexagonSubRegIndex take reference instead of pointer 

llvm-svn: 314134
This commit is contained in:
Krzysztof Parzyszek 2017-09-25 18:49:42 +00:00
parent ba3cc2e0da
commit d72bd83479
5 changed files with 17 additions and 16 deletions
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14
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
View File

@ -439,7 +439,7 @@ bool HexagonBitSimplify::parseRegSequence(const MachineInstr &I,
const MachineRegisterInfo &MRI) {
assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
auto *DstRC = MRI.getRegClass(I.getOperand(0).getReg());
auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
auto &HRI = static_cast<const HexagonRegisterInfo&>(
*MRI.getTargetRegisterInfo());
unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
@ -909,8 +909,8 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
(void)HRI;
assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) ||
Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi));
};
switch (RC->getID()) {
@ -1625,8 +1625,8 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
if (FRC == &Hexagon::DoubleRegsRegClass ||
FRC == &Hexagon::HvxWRRegClass) {
// Try to generate REG_SEQUENCE.
unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef TL = { R, SubLo };
BitTracker::RegisterRef TH = { R, SubHi };
BitTracker::RegisterRef ML, MH;
@ -1689,7 +1689,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
case TargetOpcode::REG_SEQUENCE: {
BitTracker::RegisterRef SL, SH;
if (HBS::parseRegSequence(MI, SL, SH, MRI)) {
const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI);
@ -1699,7 +1699,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
}
case Hexagon::A2_combinew:
case Hexagon::V6_vcombine: {
const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);

7
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
View File

@ -95,8 +95,8 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
if (Sub == 0)
return MachineEvaluator::mask(Reg, 0);
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
unsigned ID = RC->getID();
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
unsigned ID = RC.getID();
uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
@ -109,7 +109,8 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
break;
}
#ifndef NDEBUG
dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class "
<< TRI.getRegClassName(&RC) << '\n';
#endif
llvm_unreachable("Unexpected register/subregister");
}

2
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
View File

@ -1940,7 +1940,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
if (MI.isRegSequence()) {
unsigned Sub1 = MI.getOperand(2).getImm();
unsigned Sub2 = MI.getOperand(4).getImm();
const TargetRegisterClass *DefRC = MRI->getRegClass(DefR.Reg);
const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
if (Sub1 != SubLo && Sub1 != SubHi)

8
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -256,13 +256,13 @@ unsigned HexagonRegisterInfo::getStackRegister() const {
unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
const TargetRegisterClass *RC, unsigned GenIdx) const {
const TargetRegisterClass &RC, unsigned GenIdx) const {
assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
switch (RC->getID()) {
switch (RC.getID()) {
case Hexagon::CtrRegs64RegClassID:
case Hexagon::DoubleRegsRegClassID:
return ISub[GenIdx];
@ -270,8 +270,8 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
return VSub[GenIdx];
}
if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
return getHexagonSubRegIndex(SuperRC, GenIdx);
if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
return getHexagonSubRegIndex(*SuperRC, GenIdx);
llvm_unreachable("Invalid register class");
}

2
llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
View File

@ -67,7 +67,7 @@ public:
unsigned getFrameRegister() const;
unsigned getStackRegister() const;
unsigned getHexagonSubRegIndex(const TargetRegisterClass *RC,
unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
unsigned GenIdx) const;
const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,