forked from OSchip/llvm-project
Teach the x86 backend about the register constraints of its addressing mode.
Patch by Evan Cheng llvm-svn: 24423
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@ -17,8 +17,9 @@
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//
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class X86MemOperand<ValueType Ty> : Operand<Ty> {
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let NumMIOperands = 4;
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let PrintMethod = "printMemoryOperand";
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let NumMIOperands = 4;
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let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
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}
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def SSECC : Operand<i8> {
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let PrintMethod = "printSSECC";
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