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AMDGPU: Remove GCN features and predicates 

These are no longer necessary since the R600 tablegen files are split
out now.

llvm-svn: 353548
This commit is contained in:
Matt Arsenault 2019-02-08 19:18:01 +00:00
parent 987d331fab
commit d7047276ec
16 changed files with 18 additions and 63 deletions
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14
llvm/lib/Target/AMDGPU/AMDGPU.td
View File

@ -424,31 +424,25 @@ def FeatureDisable : SubtargetFeature<"",
"Dummy feature to disable assembler instructions"
>;
def FeatureGCN : SubtargetFeature<"gcn",
"IsGCN",
"true",
"GCN or newer GPU"
>;
class GCNSubtargetFeatureGeneration <string Value,
list<SubtargetFeature> Implies> :
SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureGCN,
FeatureWavefrontSize64,
FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
>;
def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
>;
def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
FeatureScalarStores, FeatureInv2PiInlineImm,
@ -459,7 +453,7 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
[FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,

14
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
View File

@ -65,12 +65,8 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
def TruePredicate : Predicate<"true">;
// Exists to help track down where SubtargetPredicate isn't set rather
// than letting tablegen crash with an unhelpful error.
def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
class PredicateControl {
Predicate SubtargetPredicate = InvalidPred;
Predicate SubtargetPredicate = TruePredicate;
list<Predicate> AssemblerPredicates = [];
Predicate AssemblerPredicate = TruePredicate;
list<Predicate> OtherPredicates = [];
@ -625,9 +621,7 @@ class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
: AMDGPUPat<
(sub_type (extractelt vec_type:$src, sub_idx)),
(EXTRACT_SUBREG $src, sub_reg)
> {
let SubtargetPredicate = TruePredicate;
}
>;
/* Insert element pattern */
class Insert_Element <ValueType elem_type, ValueType vec_type,
@ -635,9 +629,7 @@ class Insert_Element <ValueType elem_type, ValueType vec_type,
: AMDGPUPat <
(insertelt vec_type:$vec, elem_type:$elem, sub_idx),
(INSERT_SUBREG $vec, $elem, sub_reg)
> {
let SubtargetPredicate = TruePredicate;
}
>;
// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
// can handle COPY instructions.

4
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
View File

@ -123,6 +123,10 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
HasMovrel = true;
}
// Don't crash on invalid devices.
if (WavefrontSize == 0)
WavefrontSize = 64;
HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
return *this;

2
llvm/lib/Target/AMDGPU/DSInstructions.td
View File

@ -10,8 +10,6 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
InstSI <outs, ins, "", pattern>,
SIMCInstr <opName, SIEncodingFamily.NONE> {
let SubtargetPredicate = isGCN;
let LGKM_CNT = 1;
let DS = 1;
let Size = 8;

2
llvm/lib/Target/AMDGPU/GCNProcessors.td
View File

@ -9,7 +9,7 @@
// The code produced for "generic" is only useful for tests and cannot
// reasonably be expected to execute on any particular target.
def : ProcessorModel<"generic", NoSchedModel,
[FeatureGCN, FeatureWavefrontSize64]
[FeatureWavefrontSize64]
>;
//===----------------------------------------------------------------------===//

1
llvm/lib/Target/AMDGPU/MIMGInstructions.td
View File

@ -101,7 +101,6 @@ class MIMG <dag outs, string dns = "">
let UseNamedOperandTable = 1;
let hasSideEffects = 0; // XXX ????
let SubtargetPredicate = isGCN;
let DecoderNamespace = dns;
let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
let AsmMatchConverter = "cvtMIMG";

5
llvm/lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -10,9 +10,6 @@
//
//===----------------------------------------------------------------------===//
def isGCN : Predicate<"Subtarget->getGeneration() "
">= AMDGPUSubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureGCN">;
def isSI : Predicate<"Subtarget->getGeneration() "
"== AMDGPUSubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureSouthernIslands">;
@ -21,8 +18,6 @@ def isSI : Predicate<"Subtarget->getGeneration() "
class InstSI <dag outs, dag ins, string asm = "",
list<dag> pattern = []> :
AMDGPUInst<outs, ins, asm, pattern>, GCNPredicateControl {
let SubtargetPredicate = isGCN;
// Low bits - basic encoding information.
field bit SALU = 0;
field bit VALU = 0;

20
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
class GCNPat<dag pattern, dag result> : Pat<pattern, result>, GCNPredicateControl {
let SubtargetPredicate = isGCN;
}
include "SOPInstructions.td"
@ -581,7 +581,7 @@ def : Pat <
// VOP1 Patterns
//===----------------------------------------------------------------------===//
let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in {
let OtherPredicates = [UnsafeFPMath] in {
//def : RcpPat<V_RCP_F64_e32, f64>;
//defm : RsqPat<V_RSQ_F64_e32, f64>;
@ -604,7 +604,7 @@ def : GCNPat <
(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
>;
} // End SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath]
} // End OtherPredicates = [UnsafeFPMath]
// f16_to_fp patterns
@ -807,8 +807,6 @@ def : Pat <
(v2f16 (EXTRACT_SUBREG v4f16:$vec, sub1))
>;
let SubtargetPredicate = isGCN in {
// FIXME: Why do only some of these type combinations for SReg and
// VReg?
// 16-bit bitcast
@ -891,8 +889,6 @@ def : BitConvert <v8f32, v8i32, VReg_256>;
def : BitConvert <v16i32, v16f32, VReg_512>;
def : BitConvert <v16f32, v16i32, VReg_512>;
} // End SubtargetPredicate = isGCN
/********** =================== **********/
/********** Src & Dst modifiers **********/
/********** =================== **********/
@ -1104,9 +1100,7 @@ def : GCNPat <
/********** Intrinsic Patterns **********/
/********** ================== **********/
let SubtargetPredicate = isGCN in {
def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
}
def : GCNPat <
(i32 (sext i1:$src0)),
@ -1133,8 +1127,6 @@ def : GCNPat <
// VOP3 Patterns
//===----------------------------------------------------------------------===//
let SubtargetPredicate = isGCN in {
def : IMad24Pat<V_MAD_I32_I24, 1>;
def : UMad24Pat<V_MAD_U32_U24, 1>;
@ -1142,8 +1134,6 @@ def : UMad24Pat<V_MAD_U32_U24, 1>;
defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
def : ROTRPattern <V_ALIGNBIT_B32>;
}
def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
(V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
@ -1611,8 +1601,6 @@ multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
>;
}
let SubtargetPredicate = isGCN in {
defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
@ -1622,8 +1610,6 @@ defm : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64, SReg_64>;
defm : IntMed3Pat<V_MED3_I32, smin, smax, smin_oneuse, smax_oneuse>;
defm : IntMed3Pat<V_MED3_U32, umin, umax, umin_oneuse, umax_oneuse>;
}
// This matches 16 permutations of
// max(min(x, y), min(max(x, y), z))
class FPMed3Pat<ValueType vt,

1
llvm/lib/Target/AMDGPU/SMInstructions.td
View File

@ -33,7 +33,6 @@ class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let SchedRW = [WriteSMEM];
let SubtargetPredicate = isGCN;
string Mnemonic = opName;
string AsmOperands = asmOps;

4
llvm/lib/Target/AMDGPU/SOPInstructions.td
View File

@ -25,7 +25,6 @@ class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
let isPseudo = 1;
let isCodeGenOnly = 1;
let SubtargetPredicate = isGCN;
string Mnemonic = opName;
string AsmOperands = asmOps;
@ -556,7 +555,6 @@ class SOPK_Pseudo <string opName, dag outs, dag ins,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let SubtargetPredicate = isGCN;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@ -757,7 +755,6 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm,
let Defs = [SCC];
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
let SubtargetPredicate = isGCN;
}
class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1,
@ -855,7 +852,6 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
let SubtargetPredicate = isGCN;
}

3
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
View File

@ -229,7 +229,8 @@ unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
unsigned FlatWorkGroupSize) {
if (!STI->getFeatureBits().test(FeatureGCN))
assert(FlatWorkGroupSize != 0);
if (STI->getTargetTriple().getArch() != Triple::amdgcn)
return 8;
unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
if (N == 1)

2
llvm/lib/Target/AMDGPU/VOP1Instructions.td
View File

@ -47,7 +47,6 @@ class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1On
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SubtargetPredicate = isGCN;
let VOP1 = 1;
let VALU = 1;
@ -155,7 +154,6 @@ def V_READFIRSTLANE_B32 :
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SubtargetPredicate = isGCN;
let VOP1 = 1;
let VALU = 1;

4
llvm/lib/Target/AMDGPU/VOP2Instructions.td
View File

@ -68,7 +68,6 @@ class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suf
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SubtargetPredicate = isGCN;
let VOP2 = 1;
let VALU = 1;
@ -392,8 +391,6 @@ def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
// VOP2 Instructions
//===----------------------------------------------------------------------===//
let SubtargetPredicate = isGCN, Predicates = [isGCN] in {
defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
@ -471,7 +468,6 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16
defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
} // End SubtargetPredicate = isGCN, Predicates = [isGCN]
def : GCNPat<
(AMDGPUadde i32:$src0, i32:$src1, i1:$src2),

2
llvm/lib/Target/AMDGPU/VOPCInstructions.td
View File

@ -82,8 +82,6 @@ class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[]> :
let Uses = [EXEC];
let Defs = [VCC];
let SubtargetPredicate = isGCN;
VOPProfile Pfl = P;
}

1
llvm/lib/Target/AMDGPU/VOPInstructions.td
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@ -99,7 +99,6 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SubtargetPredicate = isGCN;
// Because SGPRs may be allowed if there are multiple operands, we
// need a post-isel hook to insert copies in order to avoid

2
llvm/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll
View File

@ -1,6 +1,6 @@
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; FUNC-LABEL: {{^}}system_acquire: