forked from OSchip/llvm-project
[AIX][PPC] Implement by-val caller arguments in multiple registers
Differential Revision: https://reviews.llvm.org/D76380
This commit is contained in:
Chris Bowler
parent
08772f1742
commit
d6ea82d11c
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@ -6866,16 +6866,16 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
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return false;
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}
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if (ByValSize <= PtrByteSize) {
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State.AllocateStack(PtrByteSize, PtrByteSize);
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if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
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return false;
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}
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}
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State.AllocateStack(alignTo(ByValSize, PtrByteSize), PtrByteSize);
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report_fatal_error(
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"Pass-by-value arguments are only supported in a single register.");
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for (unsigned I = 0, E = ByValSize; I < E; I += PtrByteSize) {
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if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32))
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
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else
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report_fatal_error(
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"Pass-by-value arguments are only supported in registers.");
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}
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return false;
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}
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// Arguments always reserve parameter save area.
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@ -7222,68 +7222,91 @@ SDValue PPCTargetLowering::LowerCall_AIX(
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: DAG.getRegister(PPC::R1, MVT::i32);
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for (unsigned I = 0, E = ArgLocs.size(); I != E;) {
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CCValAssign &VA = ArgLocs[I++];
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SDValue Arg = OutVals[VA.getValNo()];
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ISD::ArgFlagsTy Flags = Outs[VA.getValNo()].Flags;
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const MVT LocVT = VA.getLocVT();
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const MVT ValVT = VA.getValVT();
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const unsigned ValNo = ArgLocs[I].getValNo();
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SDValue Arg = OutVals[ValNo];
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ISD::ArgFlagsTy Flags = Outs[ValNo].Flags;
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if (Flags.isByVal()) {
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const unsigned ByValSize = Flags.getByValSize();
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// Nothing to do for zero-sized ByVals on the caller side.
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if (!ByValSize)
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if (!ByValSize) {
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++I;
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continue;
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}
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auto GetLoad = [&](EVT VT, unsigned LoadOffset) {
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return DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain,
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(LoadOffset != 0)
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? DAG.getObjectPtrOffset(dl, Arg, LoadOffset)
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: Arg,
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MachinePointerInfo(), VT);
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};
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unsigned LoadOffset = 0;
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// Initialize registers, which are fully occupied by the by-val argument.
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while (I != E && LoadOffset + PtrByteSize <= ByValSize) {
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SDValue Load = GetLoad(PtrVT, LoadOffset);
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MemOpChains.push_back(Load.getValue(1));
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LoadOffset += PtrByteSize;
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const CCValAssign &ByValVA = ArgLocs[I++];
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assert(ByValVA.isRegLoc() && ByValVA.getValNo() == ValNo &&
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"Unexpected location for pass-by-value argument.");
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RegsToPass.push_back(std::make_pair(ByValVA.getLocReg(), Load));
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}
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if (LoadOffset == ByValSize)
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continue;
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assert(
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VA.isRegLoc() && ByValSize <= PtrByteSize &&
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"Pass-by-value arguments are only supported in a single register.");
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const unsigned ResidueBytes = ByValSize % PtrByteSize;
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assert(ResidueBytes != 0 && LoadOffset + PtrByteSize > ByValSize &&
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"Unexpected register residue for by-value argument.");
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// Loads must be a power-of-2 size and cannot be larger than the
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// ByValSize. For example: a 7 byte by-val arg requires 4, 2 and 1 byte
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// loads.
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SDValue RegVal;
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for (unsigned Bytes = 0; Bytes != ByValSize;) {
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unsigned N = PowerOf2Floor(ByValSize - Bytes);
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// Initialize the final register residue.
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// Any residue that occupies the final by-val arg register must be
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// left-justified on AIX. Loads must be a power-of-2 size and cannot be
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// larger than the ByValSize. For example: a 7 byte by-val arg requires 4,
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// 2 and 1 byte loads.
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SDValue ResidueVal;
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for (unsigned Bytes = 0; Bytes != ResidueBytes;) {
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const unsigned N = PowerOf2Floor(ResidueBytes - Bytes);
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const MVT VT =
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N == 1 ? MVT::i8
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: ((N == 2) ? MVT::i16 : (N == 4 ? MVT::i32 : MVT::i64));
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SDValue LoadAddr = Arg;
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if (Bytes != 0) {
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// Adjust the load offset by the number of bytes read so far.
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(true);
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LoadAddr = DAG.getNode(ISD::ADD, dl, LocVT, Arg,
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DAG.getConstant(Bytes, dl, LocVT), Flags);
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}
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SDValue Load = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, LoadAddr,
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MachinePointerInfo(), VT);
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SDValue Load = GetLoad(VT, LoadOffset);
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MemOpChains.push_back(Load.getValue(1));
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LoadOffset += N;
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Bytes += N;
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assert(LocVT.getSizeInBits() >= (Bytes * 8));
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if (unsigned NumSHLBits = LocVT.getSizeInBits() - (Bytes * 8)) {
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// By-val arguments are passed left-justfied in register.
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EVT ShiftAmountTy =
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getShiftAmountTy(Load->getValueType(0), DAG.getDataLayout());
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SDValue SHLAmt = DAG.getConstant(NumSHLBits, dl, ShiftAmountTy);
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SDValue ShiftedLoad =
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DAG.getNode(ISD::SHL, dl, Load.getValueType(), Load, SHLAmt);
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RegVal = RegVal ? DAG.getNode(ISD::OR, dl, LocVT, RegVal, ShiftedLoad)
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: ShiftedLoad;
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} else {
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assert(!RegVal && Bytes == ByValSize &&
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"Pass-by-value argument handling unexpectedly incomplete.");
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RegVal = Load;
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}
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// By-val arguments are passed left-justfied in register.
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// Every load here needs to be shifted, otherwise a full register load
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// should have been used.
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assert(PtrVT.getSimpleVT().getSizeInBits() > (Bytes * 8) &&
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"Unexpected load emitted during handling of pass-by-value "
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"argument.");
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unsigned NumSHLBits = PtrVT.getSimpleVT().getSizeInBits() - (Bytes * 8);
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EVT ShiftAmountTy =
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getShiftAmountTy(Load->getValueType(0), DAG.getDataLayout());
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SDValue SHLAmt = DAG.getConstant(NumSHLBits, dl, ShiftAmountTy);
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SDValue ShiftedLoad =
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DAG.getNode(ISD::SHL, dl, Load.getValueType(), Load, SHLAmt);
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ResidueVal = ResidueVal ? DAG.getNode(ISD::OR, dl, PtrVT, ResidueVal,
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ShiftedLoad)
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: ShiftedLoad;
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}
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), RegVal));
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const CCValAssign &ByValVA = ArgLocs[I++];
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assert(ByValVA.isRegLoc() && ByValVA.getValNo() == ValNo &&
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"Additional register location expected for by-value argument.");
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RegsToPass.push_back(std::make_pair(ByValVA.getLocReg(), ResidueVal));
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continue;
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}
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CCValAssign &VA = ArgLocs[I++];
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const MVT LocVT = VA.getLocVT();
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const MVT ValVT = VA.getValVT();
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switch (VA.getLocInfo()) {
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default:
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report_fatal_error("Unexpected argument extension type.");
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@ -1,7 +1,7 @@
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; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s
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%struct.S = type { [9 x i8] }
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%struct.S = type { [65 x i8] }
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define void @bar() {
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entry:
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@ -13,4 +13,4 @@ entry:
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declare void @foo(%struct.S* byval(%struct.S) align 1)
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; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in a single register.
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; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in registers.
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@ -13,4 +13,4 @@ entry:
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declare void @foo(i32, i32, i32, i32, i32, i32, i32, i32, %struct.S* byval(%struct.S) align 1)
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; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in a single register.
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; CHECK: LLVM ERROR: Pass-by-value arguments are only supported in registers.
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@ -455,3 +455,417 @@ entry:
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; ASM64-NEXT: add [[SCRATCH3:[0-9]+]], [[SCRATCH2]], [[SCRATCH1]]
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; ASM64-NEXT: extsw 3, [[SCRATCH3]]
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; ASM64-NEXT: blr
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%struct.S5 = type { [5 x i8] }
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@gS5 = external global %struct.S5, align 1
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define void @call_test_byval_5Byte() {
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entry:
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%call = call zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
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ret void
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}
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declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
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; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
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; ASM-LABEL: .call_test_byval_5Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
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; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS5, $r2 :: (load 4 from got)
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; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LBZ 4, renamable $r[[REGADDR]] :: (load 1)
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; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
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; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7
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; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_5Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
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; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
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; CHECKASM-LABEL: .call_test_byval_5Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-DAG: lbz [[REG1:[0-9]+]], 4([[REGADDR]])
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; ASM32-DAG: lwz 3, 0([[REGADDR]])
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; ASM32-DAG: slwi 4, [[REG1]], 24
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; ASM32-NEXT: bl .test_byval_5Byte
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; ASM32-NEXT: nop
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
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; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
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; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
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; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM64: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
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; ASM64-DAG: rlwinm 3, [[REG2]], 24, 0, 7
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; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
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; ASM64-NEXT: bl .test_byval_5Byte
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; ASM64-NEXT: nop
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%struct.S6 = type { [6 x i8] }
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@gS6 = external global %struct.S6, align 1
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define void @call_test_byval_6Byte() {
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entry:
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%call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
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ret void
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}
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declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
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; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
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; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS6, $r2 :: (load 4 from got)
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; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2)
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; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
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; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15
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; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_6Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
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; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
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; CHECKASM-LABEL: .call_test_byval_6Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]])
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; ASM32-DAG: lwz 3, 0([[REGADDR]])
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; ASM32-DAG: slwi 4, [[REG1]], 16
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; ASM32-NEXT: bl .test_byval_6Byte
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; ASM32-NEXT: nop
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
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; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
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; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
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; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
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; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM64: stdu 1, -112(1)
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; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
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; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
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; ASM64-DAG: rlwinm 3, [[REG2]], 16, 0, 15
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; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
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; ASM64-NEXT: bl .test_byval_6Byte
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; ASM64-NEXT: nop
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%struct.S7 = type { [7 x i8] }
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@gS7 = external global %struct.S7, align 1
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define void @call_test_byval_7Byte() {
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entry:
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%call = call zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
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ret void
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}
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declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
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; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
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; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS7, $r2 :: (load 4 from got)
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; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
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; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2)
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; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 6, renamable $r[[REGADDR]] :: (load 1)
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; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG2]], 8, 16, 23
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; 32BIT-DAG: renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15
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; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_7Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
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; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
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; CHECKASM-LABEL: .call_test_byval_7Byte:
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; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
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; ASM32-DAG: lwz 3, 0([[REGADDR]])
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; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]])
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; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]])
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; ASM32-DAG: rlwinm 4, [[REG2]], 8, 16, 23
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; ASM32-DAG: rlwimi 4, [[REG1]], 16, 0, 15
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; ASM32-NEXT: bl .test_byval_7Byte
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; ASM32-NEXT: nop
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|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
|
||||
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
|
||||
; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
|
||||
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
|
||||
; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
|
||||
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM64: stdu 1, -112(1)
|
||||
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM64-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
|
||||
; ASM64-DAG: rlwinm 3, [[REG3]], 8, 16, 23
|
||||
; ASM64-DAG: rlwimi 3, [[REG2]], 16, 0, 15
|
||||
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM64-NEXT: bl .test_byval_7Byte
|
||||
; ASM64-NEXT: nop
|
||||
|
||||
|
||||
%struct.S8 = type { [8 x i8] }
|
||||
|
||||
@gS8 = external global %struct.S8, align 1
|
||||
|
||||
define void @call_test_byval_8Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
|
||||
; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS8, $r2 :: (load 4 from got)
|
||||
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_8Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
|
||||
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_8Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM32: stwu 1, -64(1)
|
||||
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM32-DAG: lwz 3, 0([[REGADDR]])
|
||||
; ASM32-DAG: lwz 4, 4([[REGADDR]])
|
||||
; ASM32-NEXT: bl .test_byval_8Byte
|
||||
; ASM32-NEXT: nop
|
||||
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
|
||||
; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; ASM64: stdu 1, -112(1)
|
||||
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64-NEXT: ld 3, 0([[REGADDR]])
|
||||
; ASM64-NEXT: bl .test_byval_8Byte
|
||||
; ASM64-NEXT: nop
|
||||
|
||||
|
||||
%struct.S32 = type { [32 x i8] }
|
||||
|
||||
@gS32 = external global %struct.S32, align 1
|
||||
|
||||
define void @call_test_byval_32Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 @gS32)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 %s)
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_32Byte{{.*}}
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
|
||||
; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS32, $r2 :: (load 4 from got)
|
||||
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r10 = LWZ 28, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_32Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
|
||||
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_32Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM32: stwu 1, -64(1)
|
||||
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM32-DAG: lwz 3, 0([[REGADDR]])
|
||||
; ASM32-DAG: lwz 4, 4([[REGADDR]])
|
||||
; ASM32-DAG: lwz 5, 8([[REGADDR]])
|
||||
; ASM32-DAG: lwz 6, 12([[REGADDR]])
|
||||
; ASM32-DAG: lwz 7, 16([[REGADDR]])
|
||||
; ASM32-DAG: lwz 8, 20([[REGADDR]])
|
||||
; ASM32-DAG: lwz 9, 24([[REGADDR]])
|
||||
; ASM32-DAG: lwz 10, 28([[REGADDR]])
|
||||
; ASM32-NEXT: bl .test_byval_32Byte
|
||||
; ASM32-NEXT: nop
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS32, $x2 :: (load 8 from got)
|
||||
; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_32Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; ASM64: stdu 1, -112(1)
|
||||
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64-DAG: ld 3, 0([[REGADDR]])
|
||||
; ASM64-DAG: ld 4, 8([[REGADDR]])
|
||||
; ASM64-DAG: ld 5, 16([[REGADDR]])
|
||||
; ASM64-DAG: ld 6, 24([[REGADDR]])
|
||||
; ASM64-NEXT: bl .test_byval_32Byte
|
||||
; ASM64-NEXT: nop
|
||||
|
||||
|
||||
%struct.S31 = type { [31 x i8] }
|
||||
|
||||
@gS31 = external global %struct.S31, align 1
|
||||
|
||||
define void @call_test_byval_31Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 @gS31)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare zeroext i8 @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1)
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_31Byte{{.*}}
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
|
||||
; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS31, $r2 :: (load 4 from got)
|
||||
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load 4)
|
||||
; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LHZ 28, renamable $r[[REGADDR]] :: (load 2)
|
||||
; 32BIT-DAG: renamable $r10 = LBZ 30, renamable $r[[REGADDR]] :: (load 1)
|
||||
; 32BIT-DAG: renamable $r10 = RLWINM killed renamable $r10, 8, 16, 23
|
||||
; 32BIT-DAG: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG]], 16, 0, 15
|
||||
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_31Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
|
||||
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_31Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM32: stwu 1, -64(1)
|
||||
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM32-DAG: lwz 3, 0([[REGADDR]])
|
||||
; ASM32-DAG: lwz 4, 4([[REGADDR]])
|
||||
; ASM32-DAG: lwz 5, 8([[REGADDR]])
|
||||
; ASM32-DAG: lwz 6, 12([[REGADDR]])
|
||||
; ASM32-DAG: lwz 7, 16([[REGADDR]])
|
||||
; ASM32-DAG: lwz 8, 20([[REGADDR]])
|
||||
; ASM32-DAG: lwz 9, 24([[REGADDR]])
|
||||
; ASM32-DAG: lbz 10, 30([[REGADDR]])
|
||||
; ASM32-DAG: lhz [[REG:[0-9]+]], 28([[REGADDR]])
|
||||
; ASM32-DAG: rlwinm 10, 10, 8, 16, 23
|
||||
; ASM32-DAG: rlwimi 10, [[REG]], 16, 0, 15
|
||||
; ASM32-NEXT: bl .test_byval_31Byte
|
||||
; ASM32-NEXT: nop
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS31, $x2 :: (load 8 from got)
|
||||
; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8)
|
||||
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 24, renamable $x[[REGADDR]] :: (load 4)
|
||||
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 28, renamable $x[[REGADDR]] :: (load 2)
|
||||
; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 30, renamable $x[[REGADDR]] :: (load 1)
|
||||
; 64BIT-DAG: renamable $x6 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
|
||||
; 64BIT-DAG: renamable $x6 = RLWIMI8 killed renamable $x6, killed renamable $x[[REG2]], 16, 0, 15
|
||||
; 64BIT-DAG: renamable $x6 = RLDIMI killed renamable $x6, killed renamable $x[[REG1]], 32, 0
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_31Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; ASM64: stdu 1, -112(1)
|
||||
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM64-DAG: ld 3, 0([[REGADDR]])
|
||||
; ASM64-DAG: ld 4, 8([[REGADDR]])
|
||||
; ASM64-DAG: ld 5, 16([[REGADDR]])
|
||||
; ASM64-DAG: lwz [[REG1:[0-9]+]], 24([[REGADDR]])
|
||||
; ASM64-DAG: lhz [[REG2:[0-9]+]], 28([[REGADDR]])
|
||||
; ASM64-DAG: lbz [[REG3:[0-9]+]], 30([[REGADDR]])
|
||||
; ASM64-DAG: rlwinm 6, [[REG3]], 8, 16, 23
|
||||
; ASM64-DAG: rlwimi 6, [[REG2]], 16, 0, 15
|
||||
; ASM64-DAG: rldimi 6, [[REG1]], 32, 0
|
||||
; ASM64-NEXT: bl .test_byval_31Byte
|
||||
; ASM64-NEXT: nop
|
||||
|
||||
|
||||
%struct.F = type { float, float, float }
|
||||
|
||||
define i32 @call_test_byval_homogeneous_float_struct() {
|
||||
entry:
|
||||
%s = alloca %struct.F, align 4
|
||||
%0 = bitcast %struct.F* %s to i8*
|
||||
call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 12, i1 false)
|
||||
%call = call i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) align 4 %s)
|
||||
ret i32 %call
|
||||
}
|
||||
|
||||
declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg)
|
||||
|
||||
declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) align 4)
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_homogeneous_float_struct{{.*}}
|
||||
|
||||
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
|
||||
; 32BIT-DAG: renamable $r3 = LWZ 0, %stack.0.s :: (load 4 from %stack.0.s, align 8)
|
||||
; 32BIT-DAG: renamable $r4 = LWZ 4, %stack.0.s :: (load 4 from %stack.0.s + 4)
|
||||
; 32BIT-DAG: renamable $r5 = LWZ 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
|
||||
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
|
||||
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; CHECKASM-LABEL: .call_test_byval_homogeneous_float_struct:
|
||||
|
||||
; ASM32: stwu 1, -80(1)
|
||||
; ASM32-DAG: lwz 3, 64(1)
|
||||
; ASM32-DAG: lwz 4, 68(1)
|
||||
; ASM32-DAG: lwz 5, 72(1)
|
||||
; ASM32-NEXT: bl .test_byval_homogeneous_float_struct
|
||||
; ASM32-NEXT: nop
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; 64BIT-DAG: renamable $x3 = LD 0, %stack.0.s :: (load 8 from %stack.0.s)
|
||||
; 64BIT-DAG: renamable $x4 = LWZ8 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
|
||||
; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x4, 32, 31
|
||||
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
|
||||
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM64: stdu 1, -128(1)
|
||||
; ASM64-DAG: ld 3, 112(1)
|
||||
; ASM64-DAG: lwz 4, 120(1)
|
||||
; ASM64-DAG: sldi 4, 4, 32
|
||||
; ASM64-NEXT: bl .test_byval_homogeneous_float_struct
|
||||
; ASM64-NEXT: nop
|
||||
|
|
|
|||
|
|
@ -8,39 +8,6 @@
|
|||
|
||||
%struct.S5 = type { [5 x i8] }
|
||||
|
||||
@gS5 = external global %struct.S5, align 1
|
||||
|
||||
define void @call_test_byval_5Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
|
||||
|
||||
; ASM-LABEL: .call_test_byval_5Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
|
||||
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
|
||||
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
|
||||
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM-DAG: rlwinm 3, [[REG2]], 24, 0, 7
|
||||
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM-NEXT: bl .test_byval_5Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
|
||||
define zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 %s) {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds %struct.S5, %struct.S5* %s, i32 0, i32 0, i32 4
|
||||
|
|
@ -66,39 +33,6 @@ entry:
|
|||
|
||||
%struct.S6 = type { [6 x i8] }
|
||||
|
||||
@gS6 = external global %struct.S6, align 1
|
||||
|
||||
define void @call_test_byval_6Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
|
||||
|
||||
; ASM-LABEL: .call_test_byval_6Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
|
||||
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
|
||||
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
|
||||
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM-DAG: rlwinm 3, [[REG2]], 16, 0, 15
|
||||
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM-NEXT: bl .test_byval_6Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
|
||||
define zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 %s) {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds %struct.S6, %struct.S6* %s, i32 0, i32 0, i32 5
|
||||
|
|
@ -121,45 +55,9 @@ entry:
|
|||
; ASM-NEXT: lbz 3, 53(1)
|
||||
; ASM-NEXT: blr
|
||||
|
||||
|
||||
%struct.S7 = type { [7 x i8] }
|
||||
|
||||
@gS7 = external global %struct.S7, align 1
|
||||
|
||||
define void @call_test_byval_7Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
|
||||
|
||||
; ASM-LABEL: .call_test_byval_7Byte:
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
|
||||
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
|
||||
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
|
||||
; CHECK-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
|
||||
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
|
||||
; CHECK-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
|
||||
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
|
||||
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
|
||||
; ASM-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
|
||||
; ASM-DAG: rlwinm 3, [[REG3]], 8, 16, 23
|
||||
; ASM-DAG: rlwimi 3, [[REG2]], 16, 0, 15
|
||||
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
|
||||
; ASM-NEXT: bl .test_byval_7Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
|
||||
define zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 %s) {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds %struct.S7, %struct.S7* %s, i32 0, i32 0, i32 6
|
||||
|
|
@ -185,31 +83,6 @@ entry:
|
|||
|
||||
%struct.S8 = type { [8 x i8] }
|
||||
|
||||
@gS8 = external global %struct.S8, align 1
|
||||
|
||||
define void @call_test_byval_8Byte() {
|
||||
entry:
|
||||
%call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
|
||||
|
||||
; ASM-LABEL: .call_test_byval_8Byte:
|
||||
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
|
||||
; CHECK-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-NEXT: ld 3, 0([[REGADDR]])
|
||||
; ASM-NEXT: bl .test_byval_8Byte
|
||||
; ASM-NEXT: nop
|
||||
|
||||
|
||||
define zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 %s) {
|
||||
entry:
|
||||
%arrayidx = getelementptr inbounds %struct.S8, %struct.S8* %s, i32 0, i32 0, i32 7
|
||||
|
|
@ -234,3 +107,47 @@ entry:
|
|||
; ASM-DAG: clrldi 3, 3, 56
|
||||
; ASM-DAG: std [[SCRATCH]], 48(1)
|
||||
; ASM-NEXT: blr
|
||||
|
||||
|
||||
%struct.S64 = type { [64 x i8] }
|
||||
|
||||
@gS64 = external global %struct.S64, align 1
|
||||
|
||||
define void @call_test_byval_64Byte() {
|
||||
entry:
|
||||
call void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1 @gS64)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1)
|
||||
|
||||
; CHECK-LABEL: name: call_test_byval_64Byte{{.*}}
|
||||
|
||||
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
|
||||
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
|
||||
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS64, $x2 :: (load 8 from got)
|
||||
; CHECK-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x7 = LD 32, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8)
|
||||
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_64Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
|
||||
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
|
||||
|
||||
; CHECKASM-LABEL: .test_byval_64Byte:
|
||||
|
||||
; ASM: stdu 1, -112(1)
|
||||
; ASM-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
|
||||
; ASM-DAG: ld 3, 0([[REG]])
|
||||
; ASM-DAG: ld 4, 8([[REG]])
|
||||
; ASM-DAG: ld 5, 16([[REG]])
|
||||
; ASM-DAG: ld 6, 24([[REG]])
|
||||
; ASM-DAG: ld 7, 32([[REG]])
|
||||
; ASM-DAG: ld 8, 40([[REG]])
|
||||
; ASM-DAG: ld 9, 48([[REG]])
|
||||
; ASM-DAG: ld 10, 56([[REG]])
|
||||
; ASM-NEXT: bl .test_byval_64Byte
|
||||
; ASM-NEXT: nop
|
||||
|
|
|
|||
Loading…
Reference in New Issue