forked from OSchip/llvm-project
[AMDGPU][MC] Added lds support for MUBUF instructions
See bug 28234: https://bugs.llvm.org/show_bug.cgi?id=28234 Differential Revision: https://reviews.llvm.org/D43472 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 325676
This commit is contained in:
Dmitry Preobrazhensky
parent
b21518a8cc
commit
d6e1a9404d
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@ -12,6 +12,7 @@
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "MCTargetDesc/AMDGPUTargetStreamer.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUAsmUtils.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "Utils/AMDKernelCodeTUtils.h"
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@ -128,6 +129,7 @@ public:
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enum ImmTy {
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ImmTyNone,
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ImmTyGDS,
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ImmTyLDS,
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ImmTyOffen,
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ImmTyIdxen,
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ImmTyAddr64,
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@ -303,6 +305,7 @@ public:
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bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); }
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bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); }
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bool isGDS() const { return isImmTy(ImmTyGDS); }
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bool isLDS() const { return isImmTy(ImmTyLDS); }
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bool isGLC() const { return isImmTy(ImmTyGLC); }
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bool isSLC() const { return isImmTy(ImmTySLC); }
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bool isTFE() const { return isImmTy(ImmTyTFE); }
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@ -649,6 +652,7 @@ public:
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switch (Type) {
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case ImmTyNone: OS << "None"; break;
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case ImmTyGDS: OS << "GDS"; break;
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case ImmTyLDS: OS << "LDS"; break;
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case ImmTyOffen: OS << "Offen"; break;
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case ImmTyIdxen: OS << "Idxen"; break;
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case ImmTyAddr64: OS << "Addr64"; break;
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@ -4078,6 +4082,7 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultTFE() const {
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void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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const OperandVector &Operands,
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bool IsAtomic, bool IsAtomicReturn) {
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bool HasLdsModifier = false;
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OptionalImmIndexMap OptionalIdx;
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assert(IsAtomicReturn ? IsAtomic : true);
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@ -4096,6 +4101,8 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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continue;
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}
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HasLdsModifier = Op.isLDS();
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// Handle tokens like 'offen' which are sometimes hard-coded into the
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// asm string. There are no MCInst operands for these.
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if (Op.isToken()) {
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@ -4107,6 +4114,20 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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OptionalIdx[Op.getImmTy()] = i;
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}
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// This is a workaround for an llvm quirk which may result in an
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// incorrect instruction selection. Lds and non-lds versions of
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// MUBUF instructions are identical except that lds versions
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// have mandatory 'lds' modifier. However this modifier follows
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// optional modifiers and llvm asm matcher regards this 'lds'
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// modifier as an optional one. As a result, an lds version
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// of opcode may be selected even if it has no 'lds' modifier.
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if (!HasLdsModifier) {
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int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode());
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if (NoLdsOpcode != -1) { // Got lds version - correct it.
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Inst.setOpcode(NoLdsOpcode);
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}
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}
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// Copy $vdata_in operand and insert as $vdata for MUBUF_Atomic RTN insns.
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if (IsAtomicReturn) {
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MCInst::iterator I = Inst.begin(); // $vdata_in is always at the beginning.
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@ -4118,7 +4139,10 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
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if (!HasLdsModifier) { // tfe is not legal with lds opcodes
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
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}
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}
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void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {
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@ -4312,6 +4336,7 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
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{"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr},
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{"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr},
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{"gds", AMDGPUOperand::ImmTyGDS, true, nullptr},
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{"lds", AMDGPUOperand::ImmTyLDS, true, nullptr},
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{"offset", AMDGPUOperand::ImmTyOffset, false, nullptr},
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{"inst_offset", AMDGPUOperand::ImmTyInstOffset, false, nullptr},
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{"dfmt", AMDGPUOperand::ImmTyDFMT, false, nullptr},
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@ -5022,6 +5047,8 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
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return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;
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case MCK_gds:
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return Operand.isGDS() ? Match_Success : Match_InvalidOperand;
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case MCK_lds:
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return Operand.isLDS() ? Match_Success : Match_InvalidOperand;
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case MCK_glc:
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return Operand.isGLC() ? Match_Success : Match_InvalidOperand;
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case MCK_d16:
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@ -57,6 +57,11 @@ class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
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string OpName = NAME # suffix;
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}
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class MUBUFLdsTable <bit is_lds, string suffix> {
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bit IsLds = is_lds;
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string OpName = NAME # suffix;
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}
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class MTBUFAddr64Table <bit is_addr64, string suffix = ""> {
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bit IsAddr64 = is_addr64;
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string OpName = NAME # suffix;
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@ -310,6 +315,7 @@ class MUBUF_Pseudo <string opName, dag outs, dag ins,
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bits<1> offen = 0;
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bits<1> idxen = 0;
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bits<1> addr64 = 0;
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bits<1> lds = 0;
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bits<1> has_vdata = 1;
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bits<1> has_vaddr = 1;
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bits<1> has_glc = 1;
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@ -336,7 +342,6 @@ class MUBUF_Real <bits<7> op, MUBUF_Pseudo ps> :
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bits<12> offset;
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bits<1> glc;
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bits<1> lds = 0;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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@ -371,31 +376,35 @@ class MUBUF_Invalidate <string opName, SDPatternOperator node> :
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}
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class getMUBUFInsDA<list<RegisterClass> vdataList,
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list<RegisterClass> vaddrList=[]> {
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list<RegisterClass> vaddrList=[],
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bit isLds = 0> {
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RegisterClass vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
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RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
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dag InsNoData = !if(!empty(vaddrList),
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(ins SReg_128:$srsrc, SCSrc_b32:$soffset,
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offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe),
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offset:$offset, GLC:$glc, slc:$slc),
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(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
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offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe)
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offset:$offset, GLC:$glc, slc:$slc)
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);
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dag InsData = !if(!empty(vaddrList),
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(ins vdataClass:$vdata, SReg_128:$srsrc,
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SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe),
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SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc),
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(ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
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SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc, tfe:$tfe)
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SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc)
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);
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dag ret = !if(!empty(vdataList), InsNoData, InsData);
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dag ret = !con(
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!if(!empty(vdataList), InsNoData, InsData),
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!if(isLds, (ins), (ins tfe:$tfe))
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);
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}
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class getMUBUFIns<int addrKind, list<RegisterClass> vdataList=[]> {
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class getMUBUFIns<int addrKind, list<RegisterClass> vdataList=[], bit isLds = 0> {
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dag ret =
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!if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList>.ret,
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!if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32]>.ret,
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!if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32]>.ret,
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!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64]>.ret,
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!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64]>.ret,
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!if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isLds>.ret,
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!if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32], isLds>.ret,
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!if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32], isLds>.ret,
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!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64], isLds>.ret,
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!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64], isLds>.ret,
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(ins))))));
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}
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@ -426,20 +435,28 @@ class MUBUF_Load_Pseudo <string opName,
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int addrKind,
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RegisterClass vdataClass,
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bit HasTiedDest = 0,
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bit isLds = 0,
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list<dag> pattern=[],
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// Workaround bug bz30254
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int addrKindCopy = addrKind>
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: MUBUF_Pseudo<opName,
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(outs vdataClass:$vdata),
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!con(getMUBUFIns<addrKindCopy>.ret, !if(HasTiedDest, (ins vdataClass:$vdata_in), (ins))),
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" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe",
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!con(getMUBUFIns<addrKindCopy, [], isLds>.ret,
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!if(HasTiedDest, (ins vdataClass:$vdata_in), (ins))),
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" $vdata, " # getMUBUFAsmOps<addrKindCopy>.ret # "$glc$slc" #
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!if(isLds, " lds", "$tfe"),
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pattern>,
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MUBUF_SetupAddr<addrKindCopy> {
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let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
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let PseudoInstr = opName # !if(isLds, "_lds", "") #
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"_" # getAddrName<addrKindCopy>.ret;
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let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", "");
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let mayLoad = 1;
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let mayStore = 0;
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let maybeAtomic = 1;
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let Uses = !if(isLds, [EXEC, M0], [EXEC]);
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let has_tfe = !if(isLds, 0, 1);
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let lds = isLds;
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}
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// FIXME: tfe can't be an operand because it requires a separate
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@ -447,32 +464,45 @@ class MUBUF_Load_Pseudo <string opName,
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multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
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ValueType load_vt = i32,
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SDPatternOperator ld = null_frag,
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bit TiedDest = 0> {
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bit TiedDest = 0,
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bit isLds = 0> {
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def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
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TiedDest,
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[(set load_vt:$vdata,
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(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>,
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MUBUFAddr64Table<0>;
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TiedDest, isLds,
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!if(isLds,
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[],
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[(set load_vt:$vdata,
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(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
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MUBUFAddr64Table<0, !if(isLds, "_LDS", "")>;
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def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
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TiedDest,
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[(set load_vt:$vdata,
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(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>,
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MUBUFAddr64Table<1>;
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TiedDest, isLds,
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!if(isLds,
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[],
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[(set load_vt:$vdata,
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(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
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MUBUFAddr64Table<1, !if(isLds, "_LDS", "")>;
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def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest>;
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def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest>;
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def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest>;
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def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
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def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
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def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
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let DisableWQM = 1 in {
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def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest>;
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def _OFFEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest>;
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def _IDXEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest>;
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def _BOTHEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest>;
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def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>;
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def _OFFEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
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def _IDXEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
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def _BOTHEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
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}
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}
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multiclass MUBUF_Pseudo_Loads_Lds<string opName, RegisterClass vdataClass,
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ValueType load_vt = i32,
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SDPatternOperator ld_nolds = null_frag,
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SDPatternOperator ld_lds = null_frag> {
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defm NAME : MUBUF_Pseudo_Loads<opName, vdataClass, load_vt, ld_nolds>;
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defm _LDS : MUBUF_Pseudo_Loads<opName, vdataClass, load_vt, ld_lds, 0, 1>;
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}
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class MUBUF_Store_Pseudo <string opName,
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int addrKind,
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RegisterClass vdataClass,
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@ -647,7 +677,7 @@ multiclass MUBUF_Pseudo_Atomics <string opName,
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// MUBUF Instructions
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//===----------------------------------------------------------------------===//
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defm BUFFER_LOAD_FORMAT_X : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_FORMAT_X : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_format_x", VGPR_32
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>;
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defm BUFFER_LOAD_FORMAT_XY : MUBUF_Pseudo_Loads <
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@ -726,19 +756,19 @@ let SubtargetPredicate = HasPackedD16VMem, D16 = 1 in {
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>;
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} // End HasPackedD16VMem.
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defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
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>;
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defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
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>;
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defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
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>;
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defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_sshort", VGPR_32, i32, mubuf_sextloadi16
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>;
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defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads <
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defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads_Lds <
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"buffer_load_dword", VGPR_32, i32, mubuf_load
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>;
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defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <
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@ -1582,7 +1612,7 @@ class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> :
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let Inst{13} = ps.idxen;
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let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
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let Inst{15} = ps.addr64;
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let Inst{16} = lds;
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let Inst{16} = !if(ps.lds, 1, 0);
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let Inst{24-18} = op;
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = !if(ps.has_vaddr, vaddr, ?);
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@ -1601,6 +1631,31 @@ multiclass MUBUF_Real_AllAddr_si<bits<7> op> {
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def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
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}
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multiclass MUBUF_Real_AllAddr_Lds_si<bits<7> op> {
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def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
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MUBUFLdsTable<0, "_OFFSET_si">;
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def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
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MUBUFLdsTable<0, "_ADDR64_si">;
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def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
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MUBUFLdsTable<0, "_OFFEN_si">;
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def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
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||||
MUBUFLdsTable<0, "_IDXEN_si">;
|
||||
def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
|
||||
MUBUFLdsTable<0, "_BOTHEN_si">;
|
||||
|
||||
def _LDS_OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
|
||||
MUBUFLdsTable<1, "_OFFSET_si">;
|
||||
def _LDS_ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>,
|
||||
MUBUFLdsTable<1, "_ADDR64_si">;
|
||||
def _LDS_OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
|
||||
MUBUFLdsTable<1, "_OFFEN_si">;
|
||||
def _LDS_IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
|
||||
MUBUFLdsTable<1, "_IDXEN_si">;
|
||||
def _LDS_BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
|
||||
MUBUFLdsTable<1, "_BOTHEN_si">;
|
||||
}
|
||||
|
||||
multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
|
||||
def _OFFSET_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET_RTN")>;
|
||||
def _ADDR64_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64_RTN")>;
|
||||
|
|
@ -1609,7 +1664,7 @@ multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
|
|||
def _BOTHEN_RTN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
|
||||
}
|
||||
|
||||
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_si <0x00>;
|
||||
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_si <0x00>;
|
||||
defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_si <0x01>;
|
||||
defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x02>;
|
||||
defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x03>;
|
||||
|
|
@ -1617,11 +1672,11 @@ defm BUFFER_STORE_FORMAT_X : MUBUF_Real_AllAddr_si <0x04>;
|
|||
defm BUFFER_STORE_FORMAT_XY : MUBUF_Real_AllAddr_si <0x05>;
|
||||
defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Real_AllAddr_si <0x06>;
|
||||
defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Real_AllAddr_si <0x07>;
|
||||
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_si <0x08>;
|
||||
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_si <0x09>;
|
||||
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_si <0x0a>;
|
||||
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_si <0x0b>;
|
||||
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_si <0x0c>;
|
||||
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_si <0x08>;
|
||||
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_si <0x09>;
|
||||
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_si <0x0a>;
|
||||
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_si <0x0b>;
|
||||
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_si <0x0c>;
|
||||
defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_si <0x0d>;
|
||||
defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_si <0x0e>;
|
||||
defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_si <0x0f>;
|
||||
|
|
@ -1741,7 +1796,7 @@ class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
|
|||
let Inst{12} = ps.offen;
|
||||
let Inst{13} = ps.idxen;
|
||||
let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
|
||||
let Inst{16} = lds;
|
||||
let Inst{16} = !if(ps.lds, 1, 0);
|
||||
let Inst{17} = !if(ps.has_slc, slc, ?);
|
||||
let Inst{24-18} = op;
|
||||
let Inst{31-26} = 0x38; //encoding
|
||||
|
|
@ -1759,6 +1814,27 @@ multiclass MUBUF_Real_AllAddr_vi<bits<7> op> {
|
|||
def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>;
|
||||
}
|
||||
|
||||
multiclass MUBUF_Real_AllAddr_Lds_vi<bits<7> op> {
|
||||
|
||||
def _OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
|
||||
MUBUFLdsTable<0, "_OFFSET_vi">;
|
||||
def _OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
|
||||
MUBUFLdsTable<0, "_OFFEN_vi">;
|
||||
def _IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
|
||||
MUBUFLdsTable<0, "_IDXEN_vi">;
|
||||
def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
|
||||
MUBUFLdsTable<0, "_BOTHEN_vi">;
|
||||
|
||||
def _LDS_OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
|
||||
MUBUFLdsTable<1, "_OFFSET_vi">;
|
||||
def _LDS_OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
|
||||
MUBUFLdsTable<1, "_OFFEN_vi">;
|
||||
def _LDS_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
|
||||
MUBUFLdsTable<1, "_IDXEN_vi">;
|
||||
def _LDS_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
|
||||
MUBUFLdsTable<1, "_BOTHEN_vi">;
|
||||
}
|
||||
|
||||
class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> :
|
||||
MUBUF_Real<op, ps>,
|
||||
Enc64,
|
||||
|
|
@ -1770,7 +1846,7 @@ class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> :
|
|||
let Inst{12} = ps.offen;
|
||||
let Inst{13} = ps.idxen;
|
||||
let Inst{14} = !if(ps.has_glc, glc, ps.glc_value);
|
||||
let Inst{16} = lds;
|
||||
let Inst{16} = !if(ps.lds, 1, 0);
|
||||
let Inst{17} = !if(ps.has_slc, slc, ?);
|
||||
let Inst{24-18} = op;
|
||||
let Inst{31-26} = 0x38; //encoding
|
||||
|
|
@ -1796,7 +1872,7 @@ multiclass MUBUF_Real_Atomic_vi<bits<7> op> :
|
|||
def _BOTHEN_RTN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN_RTN")>;
|
||||
}
|
||||
|
||||
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_vi <0x00>;
|
||||
defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_Lds_vi <0x00>;
|
||||
defm BUFFER_LOAD_FORMAT_XY : MUBUF_Real_AllAddr_vi <0x01>;
|
||||
defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Real_AllAddr_vi <0x02>;
|
||||
defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Real_AllAddr_vi <0x03>;
|
||||
|
|
@ -1824,11 +1900,11 @@ let SubtargetPredicate = HasPackedD16VMem in {
|
|||
defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Real_AllAddr_vi <0x0e>;
|
||||
defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Real_AllAddr_vi <0x0f>;
|
||||
} // End HasPackedD16VMem.
|
||||
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_vi <0x10>;
|
||||
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_vi <0x11>;
|
||||
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_vi <0x12>;
|
||||
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_vi <0x13>;
|
||||
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_vi <0x14>;
|
||||
defm BUFFER_LOAD_UBYTE : MUBUF_Real_AllAddr_Lds_vi <0x10>;
|
||||
defm BUFFER_LOAD_SBYTE : MUBUF_Real_AllAddr_Lds_vi <0x11>;
|
||||
defm BUFFER_LOAD_USHORT : MUBUF_Real_AllAddr_Lds_vi <0x12>;
|
||||
defm BUFFER_LOAD_SSHORT : MUBUF_Real_AllAddr_Lds_vi <0x13>;
|
||||
defm BUFFER_LOAD_DWORD : MUBUF_Real_AllAddr_Lds_vi <0x14>;
|
||||
defm BUFFER_LOAD_DWORDX2 : MUBUF_Real_AllAddr_vi <0x15>;
|
||||
defm BUFFER_LOAD_DWORDX3 : MUBUF_Real_AllAddr_vi <0x16>;
|
||||
defm BUFFER_LOAD_DWORDX4 : MUBUF_Real_AllAddr_vi <0x17>;
|
||||
|
|
|
|||
|
|
@ -915,6 +915,9 @@ namespace AMDGPU {
|
|||
LLVM_READONLY
|
||||
int getAddr64Inst(uint16_t Opcode);
|
||||
|
||||
LLVM_READONLY
|
||||
int getMUBUFNoLdsInst(uint16_t Opcode);
|
||||
|
||||
LLVM_READONLY
|
||||
int getAtomicRetOp(uint16_t Opcode);
|
||||
|
||||
|
|
|
|||
|
|
@ -2109,6 +2109,14 @@ def getAddr64Inst : InstrMapping {
|
|||
let ValueCols = [["1"]];
|
||||
}
|
||||
|
||||
def getMUBUFNoLdsInst : InstrMapping {
|
||||
let FilterClass = "MUBUFLdsTable";
|
||||
let RowFields = ["OpName"];
|
||||
let ColFields = ["IsLds"];
|
||||
let KeyCol = ["1"];
|
||||
let ValueCols = [["0"]];
|
||||
}
|
||||
|
||||
// Maps an atomic opcode to its version with a return value.
|
||||
def getAtomicRetOp : InstrMapping {
|
||||
let FilterClass = "AtomicNoRet";
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=SICI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOCI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI -check-prefix=NOSICIVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOCI -check-prefix=NOSICIVI %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI -check-prefix=NOSICIVI %s
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Test for different operand combinations
|
||||
|
|
@ -710,3 +710,69 @@ buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc
|
|||
buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc
|
||||
// SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0xf0,0xe0,0x02,0x01,0x42,0xb8]
|
||||
// VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Lds support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
buffer_load_sbyte v5, off, s[8:11], s3 lds
|
||||
// SICI: buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x25,0xe0,0x00,0x05,0x02,0x03]
|
||||
// VI: buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds
|
||||
// SICI: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x25,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds
|
||||
// SICI: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x25,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds
|
||||
// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x25,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, v0, s[8:11], s3 offen lds
|
||||
// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x25,0xe0,0x00,0x05,0x02,0x03]
|
||||
// VI: buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds
|
||||
// SICI: buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x25,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds
|
||||
// SICI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x25,0xe0,0x00,0x05,0x02,0x03]
|
||||
// VI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
|
||||
// SICI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x25,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
|
||||
// SICI: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x21,0xe0,0x00,0x05,0x02,0x03]
|
||||
// VI: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds
|
||||
// SICI: buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x2d,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds
|
||||
// SICI: buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x29,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
buffer_load_dword v5, v0, s[8:11], s101 offen lds
|
||||
// SICI: buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x31,0xe0,0x00,0x05,0x02,0x65]
|
||||
// VI: buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65]
|
||||
|
||||
buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds
|
||||
// SICI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x01,0xe0,0x00,0x05,0x42,0x03]
|
||||
// VI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Errors handling
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
buffer_load_sbyte v5, off, s[8:11], s3 lds tfe
|
||||
// NOSICIVI: error: invalid operand for instruction
|
||||
|
||||
buffer_load_dword v5, off, s[8:11], s3 tfe lds
|
||||
// NOSICIVI: error: invalid operand for instruction
|
||||
|
|
|
|||
|
|
@ -359,3 +359,46 @@
|
|||
|
||||
# VI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 idxen offen offset:4 glc slc ; encoding: [0x04,0x70,0x2e,0xe1,0x02,0x01,0x02,0xb8]
|
||||
0x04 0x70 0x2e 0xe1 0x02 0x01 0x02 0xb8
|
||||
|
||||
#===------------------------------------------------------------------------===#
|
||||
# Lds support
|
||||
#===------------------------------------------------------------------------===#
|
||||
|
||||
# VI: buffer_load_sbyte v5, off, s[8:11], s3 lds ; encoding: [0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
0x00,0x00,0x45,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds ; encoding: [0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
0x00,0x40,0x47,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc lds ; encoding: [0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x4f,0x47,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095 slc lds ; encoding: [0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x1f,0x47,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, v0, s[8:11], s3 offen lds ; encoding: [0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
0x00,0x10,0x45,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, v0, s[8:11], s3 idxen glc slc lds ; encoding: [0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
0x00,0x60,0x47,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 lds ; encoding: [0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x3f,0x45,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sbyte v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x7f,0x47,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds ; encoding: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095 glc slc lds ; encoding: [0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x5f,0x4f,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095 glc slc lds ; encoding: [0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x6f,0x4b,0xe0,0x00,0x05,0x02,0x03
|
||||
|
||||
# VI: buffer_load_dword v5, v0, s[8:11], s101 offen lds ; encoding: [0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65]
|
||||
0x00,0x10,0x51,0xe0,0x00,0x05,0x02,0x65
|
||||
|
||||
# VI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
|
||||
0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03
|
||||
|
|
|
|||
Loading…
Reference in New Issue