forked from OSchip/llvm-project
AVX512: Add store mask patterns.
Differential Revision: http://reviews.llvm.org/D16596 llvm-svn: 258914
This commit is contained in:
Igor Breger
parent
0747c5c808
commit
d6c187b038
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@ -1412,9 +1412,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
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if (Subtarget.hasDQI()) {
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setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
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@ -1708,6 +1705,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
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addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
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setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
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setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
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@ -2059,9 +2059,6 @@ let Predicates = [HasBWI] in {
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VEX, PD, VEX_W;
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defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
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VEX, XD;
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}
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let Predicates = [HasBWI] in {
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defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
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VEX, PS, VEX_W;
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defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
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@ -2101,8 +2098,27 @@ let Predicates = [HasDQI] in {
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(KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
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def : Pat<(store VK2:$src, addr:$dst),
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(KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
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def : Pat<(store VK1:$src, addr:$dst),
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(KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
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}
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let Predicates = [HasAVX512, NoDQI] in {
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def : Pat<(store VK1:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
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sub_8bit))>;
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def : Pat<(store VK2:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK2:$src, VK16)),
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sub_8bit))>;
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def : Pat<(store VK4:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK4:$src, VK16)),
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sub_8bit))>;
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def : Pat<(store VK8:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
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sub_8bit))>;
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
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def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
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@ -2182,6 +2198,17 @@ def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
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def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
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(COPY_TO_REGCLASS VK1:$src, VK64)>;
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def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
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def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
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def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
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def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
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(truncstore node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
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}]>;
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def : Pat<(truncstorei1 GR8:$src, addr:$dst),
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(MOV8mr addr:$dst, GR8:$src)>;
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// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
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let Predicates = [HasAVX512, NoDQI] in {
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@ -6562,28 +6589,6 @@ defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd
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def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
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def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
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def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
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def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
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def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
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def : Pat<(store VK1:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
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sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(store VK8:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
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sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
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def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
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(truncstore node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
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}]>;
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def : Pat<(truncstorei1 GR8:$src, addr:$dst),
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(MOV8mr addr:$dst, GR8:$src)>;
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multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
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def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
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!strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
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@ -1442,3 +1442,183 @@ define void @test23(<2 x i1> %a, <2 x i1>* %addr) {
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store <2 x i1> %a, <2 x i1>* %addr
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ret void
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}
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define void @store_v1i1(<1 x i1> %c , <1 x i1>* %ptr) {
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; KNL-LABEL: store_v1i1:
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; KNL: ## BB#0:
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; KNL-NEXT: andl $1, %edi
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; KNL-NEXT: kmovw %edi, %k0
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; KNL-NEXT: kxnorw %k0, %k0, %k1
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; KNL-NEXT: kshiftrw $15, %k1, %k1
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; KNL-NEXT: kxorw %k1, %k0, %k0
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; KNL-NEXT: kmovw %k0, %eax
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; KNL-NEXT: movb %al, (%rsi)
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; KNL-NEXT: retq
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;
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; SKX-LABEL: store_v1i1:
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; SKX: ## BB#0:
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; SKX-NEXT: andl $1, %edi
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; SKX-NEXT: kmovw %edi, %k0
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; SKX-NEXT: kxnorw %k0, %k0, %k1
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; SKX-NEXT: kshiftrw $15, %k1, %k1
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; SKX-NEXT: kxorw %k1, %k0, %k0
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; SKX-NEXT: kmovb %k0, (%rsi)
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; SKX-NEXT: retq
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%x = xor <1 x i1> %c, <i1 1>
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store <1 x i1> %x, <1 x i1>* %ptr, align 4
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ret void
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}
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define void @store_v2i1(<2 x i1> %c , <2 x i1>* %ptr) {
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; KNL-LABEL: store_v2i1:
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; KNL: ## BB#0:
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; KNL-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
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; KNL-NEXT: vpextrq $1, %xmm0, %rax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: vmovq %xmm0, %rax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: retq
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;
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; SKX-LABEL: store_v2i1:
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; SKX: ## BB#0:
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; SKX-NEXT: vpsllq $63, %xmm0, %xmm0
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; SKX-NEXT: vpmovq2m %xmm0, %k0
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; SKX-NEXT: knotw %k0, %k0
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; SKX-NEXT: kmovb %k0, (%rdi)
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; SKX-NEXT: retq
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%x = xor <2 x i1> %c, <i1 1, i1 1>
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store <2 x i1> %x, <2 x i1>* %ptr, align 4
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ret void
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}
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define void @store_v4i1(<4 x i1> %c , <4 x i1>* %ptr) {
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; KNL-LABEL: store_v4i1:
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; KNL: ## BB#0:
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; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
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; KNL-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; KNL-NEXT: vpextrd $3, %xmm0, %eax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: vpextrd $2, %xmm0, %eax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: vpextrd $1, %xmm0, %eax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: vmovd %xmm0, %eax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: retq
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;
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; SKX-LABEL: store_v4i1:
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; SKX: ## BB#0:
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; SKX-NEXT: vpslld $31, %xmm0, %xmm0
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; SKX-NEXT: vpmovd2m %xmm0, %k0
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; SKX-NEXT: knotw %k0, %k0
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; SKX-NEXT: kmovb %k0, (%rdi)
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; SKX-NEXT: retq
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%x = xor <4 x i1> %c, <i1 1, i1 1, i1 1, i1 1>
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store <4 x i1> %x, <4 x i1>* %ptr, align 4
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ret void
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}
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define void @store_v8i1(<8 x i1> %c , <8 x i1>* %ptr) {
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; KNL-LABEL: store_v8i1:
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; KNL: ## BB#0:
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; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
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; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
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; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
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; KNL-NEXT: knotw %k0, %k0
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; KNL-NEXT: kmovw %k0, %eax
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; KNL-NEXT: movb %al, (%rdi)
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; KNL-NEXT: retq
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;
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; SKX-LABEL: store_v8i1:
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; SKX: ## BB#0:
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; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
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; SKX-NEXT: vpmovw2m %xmm0, %k0
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; SKX-NEXT: knotb %k0, %k0
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; SKX-NEXT: kmovb %k0, (%rdi)
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; SKX-NEXT: retq
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%x = xor <8 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
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store <8 x i1> %x, <8 x i1>* %ptr, align 4
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ret void
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}
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define void @store_v16i1(<16 x i1> %c , <16 x i1>* %ptr) {
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; KNL-LABEL: store_v16i1:
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; KNL: ## BB#0:
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; KNL-NEXT: vpmovsxbd %xmm0, %zmm0
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; KNL-NEXT: vpslld $31, %zmm0, %zmm0
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; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
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; KNL-NEXT: knotw %k0, %k0
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; KNL-NEXT: kmovw %k0, (%rdi)
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; KNL-NEXT: retq
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;
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; SKX-LABEL: store_v16i1:
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; SKX: ## BB#0:
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; SKX-NEXT: vpsllw $7, %xmm0, %xmm0
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; SKX-NEXT: vpmovb2m %xmm0, %k0
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; SKX-NEXT: knotw %k0, %k0
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; SKX-NEXT: kmovw %k0, (%rdi)
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; SKX-NEXT: retq
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%x = xor <16 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
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store <16 x i1> %x, <16 x i1>* %ptr, align 4
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ret void
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}
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;void f2(int);
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;void f1(int c)
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;{
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; static int v = 0;
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; if (v == 0)
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; v = 1;
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; else
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; v = 0;
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; f2(v);
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;}
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@f1.v = internal unnamed_addr global i1 false, align 4
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define void @f1(i32 %c) {
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; KNL-LABEL: f1:
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; KNL: ## BB#0: ## %entry
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; KNL-NEXT: movzbl {{.*}}(%rip), %edi
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; KNL-NEXT: andl $1, %edi
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; KNL-NEXT: movl %edi, %eax
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; KNL-NEXT: andl $1, %eax
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; KNL-NEXT: kmovw %eax, %k0
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; KNL-NEXT: kxnorw %k0, %k0, %k1
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; KNL-NEXT: kshiftrw $15, %k1, %k1
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; KNL-NEXT: kxorw %k1, %k0, %k0
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; KNL-NEXT: kmovw %k0, %eax
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; KNL-NEXT: movb %al, {{.*}}(%rip)
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; KNL-NEXT: xorl $1, %edi
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; KNL-NEXT: jmp _f2 ## TAILCALL
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;
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; SKX-LABEL: f1:
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; SKX: ## BB#0: ## %entry
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; SKX-NEXT: movzbl {{.*}}(%rip), %edi
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; SKX-NEXT: andl $1, %edi
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; SKX-NEXT: movl %edi, %eax
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; SKX-NEXT: andl $1, %eax
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; SKX-NEXT: kmovw %eax, %k0
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; SKX-NEXT: kxnorw %k0, %k0, %k1
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; SKX-NEXT: kshiftrw $15, %k1, %k1
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; SKX-NEXT: kxorw %k1, %k0, %k0
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; SKX-NEXT: kmovb %k0, {{.*}}(%rip)
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; SKX-NEXT: xorl $1, %edi
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; SKX-NEXT: jmp _f2 ## TAILCALL
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entry:
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%.b1 = load i1, i1* @f1.v, align 4
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%not..b1 = xor i1 %.b1, true
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store i1 %not..b1, i1* @f1.v, align 4
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%0 = zext i1 %not..b1 to i32
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tail call void @f2(i32 %0) #2
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ret void
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}
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declare void @f2(i32) #1
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