forked from OSchip/llvm-project
[AArch64][Falkor] Refine sched details for LSLfast/ASRfast.
llvm-svn: 303682
This commit is contained in:
Geoff Berry
parent
53a21292f8
commit
d6ac96f953
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@ -763,15 +763,126 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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llvm_unreachable("Unknown opcode to check as cheap as a move!");
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}
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bool AArch64InstrInfo::isFalkorLSLFast(const MachineInstr &MI) const {
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if (MI.getNumOperands() < 4)
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bool AArch64InstrInfo::isFalkorShiftExtFast(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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unsigned ShOpVal = MI.getOperand(3).getImm();
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unsigned ShImm = AArch64_AM::getShiftValue(ShOpVal);
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if (AArch64_AM::getShiftType(ShOpVal) == AArch64_AM::LSL &&
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ShImm < 4)
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return true;
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return false;
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case AArch64::ADDWrs:
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case AArch64::ADDXrs:
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case AArch64::ADDSWrs:
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case AArch64::ADDSXrs: {
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unsigned Imm = MI.getOperand(3).getImm();
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unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
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if (ShiftVal == 0)
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return true;
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return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
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}
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case AArch64::ADDWrx:
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case AArch64::ADDXrx:
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case AArch64::ADDXrx64:
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case AArch64::ADDSWrx:
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case AArch64::ADDSXrx:
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case AArch64::ADDSXrx64: {
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unsigned Imm = MI.getOperand(3).getImm();
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switch (AArch64_AM::getArithExtendType(Imm)) {
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default:
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return false;
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case AArch64_AM::UXTB:
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case AArch64_AM::UXTH:
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case AArch64_AM::UXTW:
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case AArch64_AM::UXTX:
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return AArch64_AM::getArithShiftValue(Imm) <= 4;
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}
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}
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case AArch64::SUBWrs:
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case AArch64::SUBSWrs: {
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unsigned Imm = MI.getOperand(3).getImm();
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unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
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return ShiftVal == 0 ||
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(AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31);
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}
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case AArch64::SUBXrs:
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case AArch64::SUBSXrs: {
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unsigned Imm = MI.getOperand(3).getImm();
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unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
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return ShiftVal == 0 ||
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(AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63);
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}
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case AArch64::SUBWrx:
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case AArch64::SUBXrx:
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case AArch64::SUBXrx64:
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case AArch64::SUBSWrx:
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case AArch64::SUBSXrx:
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case AArch64::SUBSXrx64: {
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unsigned Imm = MI.getOperand(3).getImm();
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switch (AArch64_AM::getArithExtendType(Imm)) {
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default:
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return false;
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case AArch64_AM::UXTB:
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case AArch64_AM::UXTH:
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case AArch64_AM::UXTW:
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case AArch64_AM::UXTX:
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return AArch64_AM::getArithShiftValue(Imm) == 0;
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}
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}
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case AArch64::LDRBBroW:
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case AArch64::LDRBBroX:
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case AArch64::LDRBroW:
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case AArch64::LDRBroX:
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case AArch64::LDRDroW:
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case AArch64::LDRDroX:
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case AArch64::LDRHHroW:
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case AArch64::LDRHHroX:
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case AArch64::LDRHroW:
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case AArch64::LDRHroX:
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case AArch64::LDRQroW:
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case AArch64::LDRQroX:
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case AArch64::LDRSBWroW:
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case AArch64::LDRSBWroX:
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case AArch64::LDRSBXroW:
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case AArch64::LDRSBXroX:
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case AArch64::LDRSHWroW:
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case AArch64::LDRSHWroX:
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case AArch64::LDRSHXroW:
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case AArch64::LDRSHXroX:
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case AArch64::LDRSWroW:
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case AArch64::LDRSWroX:
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case AArch64::LDRSroW:
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case AArch64::LDRSroX:
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case AArch64::LDRWroW:
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case AArch64::LDRWroX:
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case AArch64::LDRXroW:
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case AArch64::LDRXroX:
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case AArch64::PRFMroW:
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case AArch64::PRFMroX:
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case AArch64::STRBBroW:
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case AArch64::STRBBroX:
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case AArch64::STRBroW:
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case AArch64::STRBroX:
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case AArch64::STRDroW:
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case AArch64::STRDroX:
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case AArch64::STRHHroW:
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case AArch64::STRHHroX:
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case AArch64::STRHroW:
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case AArch64::STRHroX:
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case AArch64::STRQroW:
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case AArch64::STRQroX:
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case AArch64::STRSroW:
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case AArch64::STRSroX:
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case AArch64::STRWroW:
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case AArch64::STRWroX:
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case AArch64::STRXroW:
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case AArch64::STRXroX: {
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unsigned IsSigned = MI.getOperand(3).getImm();
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return !IsSigned;
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}
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}
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}
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bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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@ -270,7 +270,7 @@ public:
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bool IsTailCall) const override;
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/// Returns true if the instruction has a shift by immediate that can be
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/// executed in one cycle less.
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bool isFalkorLSLFast(const MachineInstr &MI) const;
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bool isFalkorShiftExtFast(const MachineInstr &MI) const;
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private:
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/// \brief Sets the offsets on outlined instructions in \p MBB which use SP
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@ -266,14 +266,20 @@ def : InstRW<[FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc, WriteAdr],(instregex "^LD4
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// Arithmetic and Logical Instructions
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// -----------------------------------------------------------------------------
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def : InstRW<[FalkorWr_ADD], (instregex "^ADD(S)?(W|X)r(s|x)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADC(S)?(W|X)r$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADD(S)?(W|X)r(r|i)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^AND(S)?(W|X)r(i|r|s)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^BIC(S)?(W|X)r(r|s)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EON(W|X)r(r|s)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EOR(W|X)r(i|r|s)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORN(W|X)r(r|s)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORR(W|X)r(i|r|s)$")>;
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def : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^SUB(S)?(W|X)r(s|x)$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SBC(S)?(W|X)r$")>;
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def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SUB(S)?(W|X)r(r|i)$")>;
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def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>;
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def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>;
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// SIMD Miscellaneous Instructions
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// -----------------------------------------------------------------------------
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@ -328,9 +334,14 @@ def : InstRW<[FalkorWr_5VXVY_7cyc], (instregex "^TBX(v8i8Four|v16i8Four)$")>;
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// SIMD Store Instructions
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteVST], (instregex "^STP(D|S)(i)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "^STP(D|S)(post|pre)$")>;
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def : InstRW<[FalkorWr_2XYZ_2ST_2VSD_0cyc], (instregex "^STRQro(W|X)$")>;
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def : InstRW<[WriteVST], (instregex "^STR(Q|D|S|H|B)ui$")>;
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def : InstRW<[WriteVST, WriteVST], (instregex "^STPQi$")>;
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def : InstRW<[WriteVST, WriteVST, WriteAdr], (instregex "^STPQ(post|pre)$")>;
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def : InstRW<[WriteVST], (instregex "^STP(D|S)(i)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "^STP(D|S)(post|pre)$")>;
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def : InstRW<[FalkorWr_STRVro], (instregex "^STR(D|S|H|B)ro(W|X)$")>;
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def : InstRW<[FalkorWr_STRQro], (instregex "^STRQro(W|X)$")>;
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def : InstRW<[WriteVST], (instregex "^ST1(One(v8b|v4h|v2s|v1d)(_POST)?|(i8|i16|i32|i64)(_POST)?|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>;
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def : InstRW<[WriteVST], (instregex "^ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))$")>;
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@ -391,7 +402,7 @@ def : InstRW<[FalkorWr_4VXVY_3cyc], (instrs SHA256SU1rrr)>;
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def : InstRW<[WriteLD], (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>;
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def : InstRW<[WriteLD, WriteAdr], (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>;
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def : InstRW<[WriteLD], (instregex "^LDUR(Q|D|S|H|B)i$")>;
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def : InstRW<[FalkorWr_LDR], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
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def : InstRW<[FalkorWr_LDRro], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
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def : InstRW<[FalkorWr_2LD_3cyc, WriteLDHi],(instrs LDNPQi)>;
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def : InstRW<[FalkorWr_2LD_3cyc, WriteLDHi],(instrs LDPQi)>;
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def : InstRW<[FalkorWr_1LD_1none_3cyc, WriteLDHi],(instregex "LDNP(D|S)i$")>;
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@ -461,10 +472,10 @@ def : InstRW<[FalkorWr_1LD_4cyc], (instrs LDRSWl)>;
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def : InstRW<[FalkorWr_1LD_4cyc], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
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def : InstRW<[FalkorWr_1LD_4cyc], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
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def : InstRW<[FalkorWr_PRFM], (instregex "^PRFMro(W|X)$")>;
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def : InstRW<[FalkorWr_LDR], (instregex "^LDR(B|H|W|X)ro(W|X)$")>;
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def : InstRW<[FalkorWr_PRFMro], (instregex "^PRFMro(W|X)$")>;
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def : InstRW<[FalkorWr_LDRro], (instregex "^LDR(B|H|W|X)ro(W|X)$")>;
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def : InstRW<[FalkorWr_LDRS], (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
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def : InstRW<[FalkorWr_LDRSro], (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
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def : InstRW<[FalkorWr_1LD_4cyc, WriteAdr],(instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
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def : InstRW<[WriteLD, WriteLDHi, WriteAdr],(instregex "^LDP(W|X)(post|pre)$")>;
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@ -529,14 +540,9 @@ def : InstRW<[WriteVST, WriteVST], (instrs STNPQi)>;
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteST], (instregex "^STP(W|X)i$")>;
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def : InstRW<[WriteST, WriteAdr], (instregex "^STP(W|X)(post|pre)$")>;
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def : InstRW<[WriteST], (instregex "^STR(Q|D|S|BB|HH)ui$")>;
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def : InstRW<[WriteST], (instregex "^STR(BB|HH|W|X)ui$")>;
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def : InstRW<[WriteST, WriteAdr], (instregex "^STR(BB|HH|W|X)(post|pre)$")>;
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def : InstRW<[WriteST], (instregex "^STUR(Q|D|S|BB|HH)i$")>;
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def : InstRW<[WriteST], (instregex "^STR(B|H|W|X)ui$")>;
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def : InstRW<[WriteST, WriteAdr], (instregex "^STR(B|H|W|X)(post|pre)$")>;
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def : InstRW<[WriteST], (instregex "^STTR(B|H|W|X)i$")>;
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def : InstRW<[WriteST], (instregex "^STUR(B|H|W|X)i$")>;
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def : InstRW<[WriteST, WriteAdr], (instregex "^STR(B|H|W|X)ro(W|X)$")>;
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def : InstRW<[WriteVST, WriteVST], (instregex "^STPQi$")>;
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def : InstRW<[WriteVST, WriteVST, WriteAdr], (instregex "^STPQ(post|pre)$")>;
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def : InstRW<[FalkorWr_STRro], (instregex "^STR(B|H|W|X)ro(W|X)$")>;
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@ -186,6 +186,11 @@ def FalkorWr_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitSD, FalkorUnitST]> {
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let NumMicroOps = 2;
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}
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def FalkorWr_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitVSD, FalkorUnitST]> {
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let Latency = 0;
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let NumMicroOps = 2;
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}
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//===----------------------------------------------------------------------===//
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// Define 3 micro-op types
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@ -243,6 +248,14 @@ def FalkorWr_2LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
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let NumMicroOps = 3;
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}
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def FalkorWr_1XYZ_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitSD, FalkorUnitST]> {
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let Latency = 0;
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let NumMicroOps = 3;
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}
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def FalkorWr_1XYZ_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitVSD, FalkorUnitST]> {
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let Latency = 0;
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let NumMicroOps = 3;
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}
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//===----------------------------------------------------------------------===//
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// Define 4 micro-op types
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@ -316,6 +329,12 @@ def FalkorWr_5VXVY_7cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY,
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let Latency = 7;
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let NumMicroOps = 5;
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}
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def FalkorWr_1XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST,
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FalkorUnitVSD, FalkorUnitST,
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FalkorUnitVSD]> {
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let Latency = 0;
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let NumMicroOps = 5;
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}
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//===----------------------------------------------------------------------===//
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// Define 6 micro-op types
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@ -373,12 +392,12 @@ def FalkorReadVMA : SchedReadAdvance<3, [FalkorWr_VMUL32_1VXVY_4cyc, FalkorWr
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def FalkorReadFMA32 : SchedReadAdvance<1, [FalkorWr_FMUL32_1VXVY_5cyc, FalkorWr_FMUL32_2VXVY_5cyc]>;
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def FalkorReadFMA64 : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr_FMUL64_2VXVY_6cyc]>;
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// SchedPredicates and WriteVariants for Immediate Zero and LSLFast
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// SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast
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// -----------------------------------------------------------------------------
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def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>;
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def FalkorFMOVZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR ||
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MI->getOperand(1).getReg() == AArch64::XZR}]>;
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def FalkorLSLFastPred : SchedPredicate<[{TII->isFalkorLSLFast(*MI)}]>;
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def FalkorShiftExtFastPred : SchedPredicate<[{TII->isFalkorShiftExtFast(*MI)}]>;
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def FalkorWr_FMOV : SchedWriteVariant<[
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SchedVar<FalkorFMOVZrReg, [FalkorWr_1none_0cyc]>,
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@ -388,18 +407,31 @@ def FalkorWr_MOVZ : SchedWriteVariant<[
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SchedVar<FalkorImmZPred, [FalkorWr_1none_0cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZB_1cyc]>]>;
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def FalkorWr_LDR : SchedWriteVariant<[
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SchedVar<FalkorLSLFastPred, [FalkorWr_1LD_3cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_4cyc]>]>;
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def FalkorWr_ADDSUBsx : SchedWriteVariant<[
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SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_1cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_2XYZ_2cyc]>]>;
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def FalkorWr_ADD : SchedWriteVariant<[
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SchedVar<FalkorLSLFastPred, [FalkorWr_1XYZ_1cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_2XYZ_2cyc]>]>;
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def FalkorWr_LDRro : SchedWriteVariant<[
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SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_3cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_4cyc]>]>;
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def FalkorWr_PRFM : SchedWriteVariant<[
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SchedVar<FalkorLSLFastPred, [FalkorWr_1ST_3cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZ_1ST_4cyc]>]>;
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def FalkorWr_LDRSro : SchedWriteVariant<[
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SchedVar<FalkorShiftExtFastPred, [FalkorWr_1LD_4cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_5cyc]>]>;
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def FalkorWr_PRFMro : SchedWriteVariant<[
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SchedVar<FalkorShiftExtFastPred, [FalkorWr_1ST_3cyc]>,
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SchedVar<NoSchedPred, [FalkorWr_1XYZ_1ST_4cyc]>]>;
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def FalkorWr_STRVro : SchedWriteVariant<[
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||||
SchedVar<FalkorShiftExtFastPred, [FalkorWr_1VSD_1ST_0cyc]>,
|
||||
SchedVar<NoSchedPred, [FalkorWr_1XYZ_1VSD_1ST_0cyc]>]>;
|
||||
|
||||
def FalkorWr_STRQro : SchedWriteVariant<[
|
||||
SchedVar<FalkorShiftExtFastPred, [FalkorWr_1XYZ_2ST_2VSD_0cyc]>,
|
||||
SchedVar<NoSchedPred, [FalkorWr_2XYZ_2ST_2VSD_0cyc]>]>;
|
||||
|
||||
def FalkorWr_STRro : SchedWriteVariant<[
|
||||
SchedVar<FalkorShiftExtFastPred, [FalkorWr_1SD_1ST_0cyc]>,
|
||||
SchedVar<NoSchedPred, [FalkorWr_1XYZ_1SD_1ST_0cyc]>]>;
|
||||
|
||||
def FalkorWr_LDRS : SchedWriteVariant<[
|
||||
SchedVar<FalkorLSLFastPred, [FalkorWr_1LD_4cyc]>,
|
||||
SchedVar<NoSchedPred, [FalkorWr_1XYZ_1LD_5cyc]>]>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue