From d6ac8f5e5a4b717f2319a200b727d17d232e2e81 Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Thu, 14 Oct 2004 05:54:38 +0000
Subject: [PATCH] PowerPC instruction definitions use LittleEndian-style
 encoding [0..31]

llvm-svn: 16977
---
 llvm/lib/Target/PowerPC/PPC32.td   | 2 ++
 llvm/lib/Target/PowerPC/PPC64.td   | 2 ++
 llvm/lib/Target/PowerPC/PowerPC.td | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/llvm/lib/Target/PowerPC/PPC32.td b/llvm/lib/Target/PowerPC/PPC32.td
index bd6afd9dc876..fb115f431295 100644
--- a/llvm/lib/Target/PowerPC/PPC32.td
+++ b/llvm/lib/Target/PowerPC/PPC32.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PPC32 : Target {
diff --git a/llvm/lib/Target/PowerPC/PPC64.td b/llvm/lib/Target/PowerPC/PPC64.td
index 264a261f368f..06067ed1f41b 100644
--- a/llvm/lib/Target/PowerPC/PPC64.td
+++ b/llvm/lib/Target/PowerPC/PPC64.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PPC64 : Target {
diff --git a/llvm/lib/Target/PowerPC/PowerPC.td b/llvm/lib/Target/PowerPC/PowerPC.td
index f556aeeae77b..b7d5bf116f88 100644
--- a/llvm/lib/Target/PowerPC/PowerPC.td
+++ b/llvm/lib/Target/PowerPC/PowerPC.td
@@ -27,6 +27,8 @@ def PowerPCInstrInfo : InstrInfo {
   let TSFlagsFields = ["ArgCount", "Arg0Type", "Arg1Type", "Arg2Type", 
                        "Arg3Type", "Arg4Type", "VMX", "PPC64"];
   let TSFlagsShifts = [ 0, 3, 8, 13, 18, 23, 28, 29 ];
+
+  let isLittleEndianEncoding = 1;
 }
 
 def PowerPC : Target {