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AMDGPU/GlobalISel: Simplify code 

This can directly access the register bank, and doesn't need to get it
through the ID.
This commit is contained in:
Matt Arsenault 2019-12-20 18:55:41 +05:30 committed by Matt Arsenault
parent 7ece0ee3dd
commit d688a6739d
1 changed files with 5 additions and 5 deletions
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10
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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@ -928,7 +928,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
Op.setReg(Merge.getReg(0));
}
MRI.setRegBank(Op.getReg(), getRegBank(AMDGPU::SGPRRegBankID));
MRI.setRegBank(Op.getReg(), AMDGPU::SGPRRegBank);
}
}
}
@ -1117,11 +1117,11 @@ bool AMDGPURegisterBankInfo::applyMappingWideLoad(MachineInstr &MI,
for (unsigned DefIdx = 0, e = DefRegs.size(); DefIdx != e; ++DefIdx) {
Register IdxReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
B.buildConstant(IdxReg, DefIdx);
MRI.setRegBank(IdxReg, getRegBank(AMDGPU::VGPRRegBankID));
MRI.setRegBank(IdxReg, AMDGPU::VGPRRegBank);
B.buildExtractVectorElement(DefRegs[DefIdx], TmpReg, IdxReg);
}
MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
return true;
}
@ -1389,7 +1389,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
B.buildSelect(DefRegs[0], Src0Regs[0], Src1Regs[0], Src2Regs[0]);
B.buildSelect(DefRegs[1], Src0Regs[0], Src1Regs[1], Src2Regs[1]);
MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
MI.eraseFromParent();
return;
}
@ -1445,7 +1445,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
.addUse(Src0Regs[1])
.addUse(Src1Regs[1]);
MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
MI.eraseFromParent();
return;
}