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[AArch64][CodeGen] Restrict bfloat vector operations to what's actually supported 

Previously in addTypeForNeon, we would set the operations for bfloat vectors
like other generic types. But as bfloat is a storage-only type a number of
operations shouldn't be set. This patch fixes that.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D85101
This commit is contained in:
Ties Stuij 2020-08-28 09:31:11 +01:00
parent 96824abe7d
commit d678e14c55
4 changed files with 9 additions and 6 deletions
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7
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -176,7 +176,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
addDRTypeForNEON(MVT::v1i64);
addDRTypeForNEON(MVT::v1f64);
addDRTypeForNEON(MVT::v4f16);
addDRTypeForNEON(MVT::v4bf16);
if (Subtarget->hasBF16())
addDRTypeForNEON(MVT::v4bf16);
addQRTypeForNEON(MVT::v4f32);
addQRTypeForNEON(MVT::v2f64);
@ -185,7 +186,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
addQRTypeForNEON(MVT::v4i32);
addQRTypeForNEON(MVT::v2i64);
addQRTypeForNEON(MVT::v8f16);
addQRTypeForNEON(MVT::v8bf16);
if (Subtarget->hasBF16())
addQRTypeForNEON(MVT::v8bf16);
}
if (Subtarget->hasSVE()) {
@ -1096,6 +1098,7 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
// F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
if (VT.isFloatingPoint() &&
VT.getVectorElementType() != MVT::bf16 &&
(VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
for (unsigned Opcode :
{ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})

2
llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi | FileCheck %s
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v4i16:

2
llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi | FileCheck %s
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
; bfloat16x4_t test_vcreate_bf16(uint64_t a) { return vcreate_bf16(a); }
define <4 x bfloat> @test_vcreate_bf16(i64 %a) nounwind {

4
llvm/test/CodeGen/AArch64/bf16.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -asm-verbose=0 -mtriple=arm64-eabi | FileCheck %s
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-eabi | FileCheck %s
; RUN: llc < %s -asm-verbose=0 -mtriple=arm64-eabi -mattr=+bf16 | FileCheck %s
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-eabi -mattr=+bf16 | FileCheck %s
; test argument passing and simple load/store