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[SelectionDAG] Correct the early out in SelectionDAG::getZeroExtendInReg to work properly for vector types. 

I don't know if we ever hit this case or not. Turning it into an assert only fired on expanding some atomic operation in a SystemZ lit test.

llvm-svn: 315648
This commit is contained in:
Craig Topper 2017-10-13 00:18:58 +00:00
parent 8bc23ab658
commit d6630b9889
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1027,7 +1027,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
assert(!VT.isVector() &&
"getZeroExtendInReg should use the vector element type instead of "
"the vector type!");
if (Op.getValueType() == VT) return Op;
if (Op.getValueType().getScalarType() == VT) return Op;
unsigned BitWidth = Op.getScalarValueSizeInBits();
APInt Imm = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());