forked from OSchip/llvm-project
AArch64/GlobalISel: Reduce use of getMinClassForRegBank
getMinClassForRegBank and getRegClassForTypeOnBank were basically identical functions with different APIs. Consolidate on the version that uses LLT instead of a bitwidth, since that would be more appropriate to use in a generic API. Keep getMinClassForRegBank around for now, since copies are a special case that can't simply read the type from the register operands.
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@ -507,9 +507,11 @@ AArch64InstructionSelector::AArch64InstructionSelector(
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// FIXME: This should be target-independent, inferred from the types declared
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// for each class in the bank.
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//
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/// Given a register bank, and a type, return the smallest register class that
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/// can represent that combination.
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static const TargetRegisterClass *
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getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
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const RegisterBankInfo &RBI,
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bool GetAllRegSet = false) {
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if (RB.getID() == AArch64::GPRRegBankID) {
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if (Ty.getSizeInBits() <= 32)
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@ -1854,7 +1856,7 @@ bool AArch64InstructionSelector::selectVectorAshrLshr(
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unsigned Opc = 0;
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unsigned NegOpc = 0;
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const TargetRegisterClass *RC =
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getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI);
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getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID));
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if (Ty == LLT::fixed_vector(2, 64)) {
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Opc = IsASHR ? AArch64::SSHLv2i64 : AArch64::USHLv2i64;
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NegOpc = AArch64::NEGv2i64;
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@ -2356,7 +2358,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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return false;
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}
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const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
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DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
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DefRC = getRegClassForTypeOnBank(DefTy, RB);
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if (!DefRC) {
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LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
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return false;
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@ -2554,7 +2556,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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if (isFP) {
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const TargetRegisterClass &FPRRC = *getMinClassForRegBank(RB, DefSize);
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const TargetRegisterClass &FPRRC = *getRegClassForTypeOnBank(DefTy, RB);
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// For 16, 64, and 128b values, emit a constant pool load.
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switch (DefSize) {
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default:
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@ -2818,7 +2820,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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if (isa<GStore>(LdSt) && ValTy.getSizeInBits() > MemSizeInBits) {
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unsigned SubReg;
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LLT MemTy = LdSt.getMMO().getMemoryType();
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auto *RC = getRegClassForTypeOnBank(MemTy, RB, RBI);
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auto *RC = getRegClassForTypeOnBank(MemTy, RB);
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if (!getSubRegForClass(RC, TRI, SubReg))
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return false;
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@ -2834,7 +2836,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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if (RB.getID() == AArch64::FPRRegBankID) {
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unsigned SubReg;
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LLT MemTy = LdSt.getMMO().getMemoryType();
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auto *RC = getRegClassForTypeOnBank(MemTy, RB, RBI);
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auto *RC = getRegClassForTypeOnBank(MemTy, RB);
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if (!getSubRegForClass(RC, TRI, SubReg))
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return false;
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Register OldDst = LdSt.getReg(0);
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@ -2848,7 +2850,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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.addImm(0)
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.addUse(NewDst)
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.addImm(SubReg);
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auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB, RBI);
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auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB);
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RBI.constrainGenericRegister(OldDst, *SubRegRC, MRI);
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MIB.setInstr(LdSt);
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}
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@ -3064,13 +3066,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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if (DstRB.getID() == AArch64::GPRRegBankID) {
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(DstTy, DstRB, RBI);
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const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
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if (!DstRC)
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return false;
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const TargetRegisterClass *SrcRC =
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getRegClassForTypeOnBank(SrcTy, SrcRB, RBI);
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const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB);
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if (!SrcRC)
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return false;
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@ -3397,8 +3397,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
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const Register DstReg = I.getOperand(0).getReg();
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const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(DstTy, DstRB, RBI);
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const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
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RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
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return true;
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}
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@ -3911,7 +3910,7 @@ bool AArch64InstructionSelector::selectVectorICmp(
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const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC =
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getRegClassForTypeOnBank(SrcTy, VecRB, RBI, true);
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getRegClassForTypeOnBank(SrcTy, VecRB, true);
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if (!SrcRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return false;
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@ -4077,7 +4076,7 @@ MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
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}
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const TargetRegisterClass *DstRC =
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getRegClassForTypeOnBank(ScalarTy, DstRB, RBI, true);
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getRegClassForTypeOnBank(ScalarTy, DstRB, true);
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if (!DstRC) {
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LLVM_DEBUG(dbgs() << "Could not determine destination register class.\n");
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return nullptr;
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@ -4086,7 +4085,7 @@ MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
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const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);
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const LLT &VecTy = MRI.getType(VecReg);
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const TargetRegisterClass *VecRC =
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getRegClassForTypeOnBank(VecTy, VecRB, RBI, true);
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getRegClassForTypeOnBank(VecTy, VecRB, true);
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if (!VecRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return nullptr;
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@ -4245,9 +4244,9 @@ bool AArch64InstructionSelector::selectUnmergeValues(MachineInstr &I,
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} else {
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// No. We have to perform subregister inserts. For each insert, create an
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// implicit def and a subregister insert, and save the register we create.
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const TargetRegisterClass *RC =
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getMinClassForRegBank(*RBI.getRegBank(SrcReg, MRI, TRI),
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WideTy.getScalarSizeInBits() * NumElts);
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const TargetRegisterClass *RC = getRegClassForTypeOnBank(
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LLT::fixed_vector(NumElts, WideTy.getScalarSizeInBits()),
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*RBI.getRegBank(SrcReg, MRI, TRI));
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unsigned SubReg = 0;
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bool Found = getSubRegForClass(RC, TRI, SubReg);
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(void)Found;
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@ -4673,7 +4672,7 @@ MachineInstr *AArch64InstructionSelector::emitVectorConcat(
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const LLT ScalarTy = LLT::scalar(Op1Ty.getSizeInBits());
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const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getMinClassForRegBank(FPRBank, Op1Ty.getSizeInBits() * 2);
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getRegClassForTypeOnBank(Op1Ty.multiplyElements(2), FPRBank);
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MachineInstr *WidenedOp1 =
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emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder);
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@ -5371,7 +5370,7 @@ bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I,
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// the original size to get the result we want.
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Register DemoteVec = InsMI->getOperand(0).getReg();
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const TargetRegisterClass *RC =
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getMinClassForRegBank(*RBI.getRegBank(DemoteVec, MRI, TRI), VecSize);
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getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DemoteVec, MRI, TRI));
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if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
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LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
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return false;
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@ -5488,12 +5487,11 @@ bool AArch64InstructionSelector::tryOptBuildVecToSubregToReg(
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}))
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return false;
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unsigned SubReg;
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const TargetRegisterClass *EltRC =
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getMinClassForRegBank(EltRB, EltTy.getSizeInBits());
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const TargetRegisterClass *EltRC = getRegClassForTypeOnBank(EltTy, EltRB);
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if (!EltRC)
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return false;
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const TargetRegisterClass *DstRC =
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getMinClassForRegBank(DstRB, MRI.getType(Dst).getSizeInBits());
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getRegClassForTypeOnBank(MRI.getType(Dst), DstRB);
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if (!DstRC)
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return false;
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if (!getSubRegForClass(EltRC, TRI, SubReg))
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@ -5551,7 +5549,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
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if (DstSize < 128) {
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// Force this to be FPR using the destination vector.
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const TargetRegisterClass *RC =
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getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
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getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI));
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if (!RC)
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return false;
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if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
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