forked from OSchip/llvm-project
GlobalISel: Fix artifact combiner constant legality checks for vectors
Since G_CONSTANT is illegal for vectors, this needs to check what buildConstant will produce for a splat vector. llvm-svn: 353449
This commit is contained in:
Matt Arsenault
parent
954966c1af
commit
d6212f9f1b
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@ -80,11 +80,11 @@ public:
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if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
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LLT DstTy = MRI.getType(DstReg);
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if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
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isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
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isConstantUnsupported(DstTy))
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return false;
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LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
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LLT SrcTy = MRI.getType(SrcReg);
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APInt Mask = APInt::getAllOnesValue(SrcTy.getSizeInBits());
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APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
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auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue());
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Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
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MIBMask);
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@ -112,11 +112,11 @@ public:
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// applicable.
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if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy, DstTy}}) ||
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isInstUnsupported({TargetOpcode::G_ASHR, {DstTy, DstTy}}) ||
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isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
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isConstantUnsupported(DstTy))
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return false;
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LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
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LLT SrcTy = MRI.getType(SrcReg);
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unsigned ShAmt = DstTy.getSizeInBits() - SrcTy.getSizeInBits();
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unsigned ShAmt = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();
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auto MIBShAmt = Builder.buildConstant(DstTy, ShAmt);
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auto MIBShl = Builder.buildInstr(
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TargetOpcode::G_SHL, {DstTy},
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@ -151,7 +151,7 @@ public:
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} else {
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// G_[SZ]EXT (G_IMPLICIT_DEF) -> G_CONSTANT 0 because the top
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// bits will be 0 for G_ZEXT and 0/1 for the G_SEXT.
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if (isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
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if (isConstantUnsupported(DstTy))
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return false;
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LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI;);
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Builder.buildConstant(DstReg, 0);
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@ -403,6 +403,15 @@ private:
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return Step.Action == Unsupported || Step.Action == NotFound;
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}
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bool isConstantUnsupported(LLT Ty) const {
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if (!Ty.isVector())
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return isInstUnsupported({TargetOpcode::G_CONSTANT, {Ty}});
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LLT EltTy = Ty.getElementType();
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return isInstUnsupported({TargetOpcode::G_CONSTANT, {EltTy}}) ||
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isInstUnsupported({TargetOpcode::G_BUILD_VECTOR, {Ty, EltTy}});
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}
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/// Looks through copy instructions and returns the actual
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/// source register.
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unsigned lookThroughCopyInstrs(unsigned Reg) {
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@ -0,0 +1,70 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
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---
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name: test_anyext_trunc_v2s32_to_v2s16_to_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s16_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
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; CHECK: $vgpr0_vgpr1 = COPY [[COPY1]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s32>) = G_ANYEXT %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_anyext_trunc_v2s32_to_v2s16_to_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s16_to_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s64>) = G_ANYEXT %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s8_to_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
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; CHECK: $vgpr0 = COPY [[TRUNC]](<2 x s16>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s8>) = G_TRUNC %0
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%2:_(<2 x s16>) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2
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; CHECK-LABEL: name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](<3 x s32>)
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%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(<3 x s16>) = G_TRUNC %0
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%2:_(<3 x s32>) = G_ANYEXT %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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@ -0,0 +1,99 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
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---
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name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
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; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s32>) = G_SEXT %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
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; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
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; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT1]], [[TRUNC1]](s32)
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
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; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC2]](s32)
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; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
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; CHECK: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[TRUNC3]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s64>) = G_SEXT %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
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; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
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; CHECK: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[TRUNC]], [[BUILD_VECTOR]](<2 x s16>)
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; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s16>)
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; CHECK: $vgpr0 = COPY [[ASHR]](<2 x s16>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s8>) = G_TRUNC %0
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%2:_(<2 x s16>) = G_SEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2
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; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
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; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
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; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
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; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
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%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(<3 x s16>) = G_TRUNC %0
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%2:_(<3 x s32>) = G_SEXT %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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@ -0,0 +1,85 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
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---
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name: test_zext_trunc_v2s32_to_v2s16_to_v2s32
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s16_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
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; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
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; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s32>) = G_ZEXT %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_zext_trunc_v2s32_to_v2s16_to_v2s64
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s16_to_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
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; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[AND]](s64), [[AND1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s16>) = G_TRUNC %0
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%2:_(<2 x s64>) = G_ZEXT %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
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; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
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; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC]], [[BUILD_VECTOR]]
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; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s8>) = G_TRUNC %0
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||||
%2:_(<2 x s16>) = G_ZEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_zext_trunc_v3s32_to_v3s16_to_v3s32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2
|
||||
|
||||
; CHECK-LABEL: name: test_zext_trunc_v3s32_to_v3s16_to_v3s32
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
|
||||
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
|
||||
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
|
||||
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
|
||||
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
|
||||
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
||||
%1:_(<3 x s16>) = G_TRUNC %0
|
||||
%2:_(<3 x s32>) = G_ZEXT %1
|
||||
$vgpr0_vgpr1_vgpr2 = COPY %2
|
||||
...
|
||||
|
|
@ -187,12 +187,8 @@ body: |
|
|||
bb.0:
|
||||
|
||||
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
|
||||
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s8>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](<2 x s8>)
|
||||
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s8)
|
||||
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s8)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
|
||||
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[COPY]](s32)
|
||||
|
|
@ -229,12 +225,8 @@ body: |
|
|||
bb.0:
|
||||
|
||||
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
|
||||
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
|
||||
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
|
||||
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
|
||||
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[COPY]](s32)
|
||||
|
|
@ -252,14 +244,11 @@ body: |
|
|||
bb.0:
|
||||
|
||||
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
|
||||
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
|
||||
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
|
||||
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
|
||||
; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
|
||||
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT2]](s32)
|
||||
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
|
||||
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
|
||||
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[COPY]](s32)
|
||||
%0:_(<2 x s1>) = G_IMPLICIT_DEF
|
||||
|
|
|
|||
Loading…
Reference in New Issue