forked from OSchip/llvm-project
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debe69fb37
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@ -385,24 +385,13 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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}
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
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[(ARMretflag)]>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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let Inst{6-3} = 0b1110; // Rm = lr
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let Inst{2-0} = 0b000;
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}
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def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br,
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[(ARMretflag)], (tBX LR, (ops 14, zero_reg))>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
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IIC_Br, "bx\t$Rm",
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[]>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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let Inst{2-0} = 0b000;
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}
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def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm),
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Size2Bytes, IIC_Br, [],
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(tBX GPR:$Rm, (ops 14, zero_reg))>;
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}
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// All calls clobber the non-callee saved registers. SP is marked as a use to
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