forked from OSchip/llvm-project
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commit
d5ebba2aa6
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@ -338,6 +338,41 @@ define i32 @multi_use_load_scalarization(<4 x i32>* %p) nounwind {
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ret i32 %r
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}
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define i32 @multi_use_volatile_load_scalarization(<4 x i32>* %p) nounwind {
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; X32-SSE2-LABEL: multi_use_volatile_load_scalarization:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: movl (%ecx), %eax
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; X32-SSE2-NEXT: movdqu (%ecx), %xmm0
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; X32-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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; X32-SSE2-NEXT: psubd %xmm1, %xmm0
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; X32-SSE2-NEXT: movdqa %xmm0, (%ecx)
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: multi_use_volatile_load_scalarization:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: movl (%rdi), %eax
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; X64-SSSE3-NEXT: movdqu (%rdi), %xmm0
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; X64-SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
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; X64-SSSE3-NEXT: psubd %xmm1, %xmm0
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; X64-SSSE3-NEXT: movdqa %xmm0, (%rdi)
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: multi_use_volatile_load_scalarization:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: movl (%rdi), %eax
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; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0
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; X64-AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; X64-AVX-NEXT: vmovdqa %xmm0, (%rdi)
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; X64-AVX-NEXT: retq
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%v = load volatile <4 x i32>, <4 x i32>* %p, align 1
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%v1 = add <4 x i32> %v, <i32 1, i32 1, i32 1, i32 1>
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store <4 x i32> %v1, <4 x i32>* %p
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%r = extractelement <4 x i32> %v, i64 0
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ret i32 %r
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}
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; This test is reduced from a C source example that showed a miscompile:
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; https://github.com/llvm/llvm-project/issues/53695
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; The scalarized loads from 'zero' in the AVX asm must occur before
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