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[X86] Merge instregex patterns to reduce InstrRW compile time. 

llvm-svn: 331911
This commit is contained in:
Simon Pilgrim 2018-05-09 19:04:15 +00:00
parent b89605db01
commit d5d4cdb49d
5 changed files with 365 additions and 1052 deletions
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57
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

@ -566,15 +566,11 @@ def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
"MOVNTI_64mr", "MOVNTI_64mr",
"MOVNTImr", "MOVNTImr",
"ST_FP(32|64|80)m", "ST_FP(32|64|80)m",
"(V?)MOVHPDmr", "(V?)MOV(H|L)(PD|PS)mr",
"(V?)MOVHPSmr",
"(V?)MOVLPDmr",
"(V?)MOVLPSmr",
"(V?)MOVPDI2DImr", "(V?)MOVPDI2DImr",
"(V?)MOVPQI2QImr", "(V?)MOVPQI2QImr",
"(V?)MOVPQIto64mr", "(V?)MOVPQIto64mr",
"(V?)MOVSDmr", "(V?)MOV(SD|SS)mr")>;
"(V?)MOVSSmr")>;
def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
let Latency = 2; let Latency = 2;
@ -778,14 +774,10 @@ def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr", def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
"(V?)CVTSD2SIrr", "(V?)CVT(T?)SD2SIrr",
"(V?)CVTSS2SI64rr", "(V?)CVT(T?)SS2SI64rr",
"(V?)CVTSS2SIrr", "(V?)CVT(T?)SS2SIrr")>;
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr",
"(V?)CVTTSS2SI64rr",
"(V?)CVTTSS2SIrr")>;
def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
let Latency = 4; let Latency = 4;
@ -807,20 +799,17 @@ def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>; def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr", def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr",
"MMX_CVTPI2PDirr", "MMX_CVT(T?)PD2PIirr",
"MMX_CVTPS2PIirr", "MMX_CVT(T?)PS2PIirr",
"MMX_CVTTPD2PIirr",
"MMX_CVTTPS2PIirr",
"(V?)CVTDQ2PDrr", "(V?)CVTDQ2PDrr",
"(V?)CVTPD2DQrr",
"(V?)CVTPD2PSrr", "(V?)CVTPD2PSrr",
"VCVTPS2PHrr", "VCVTPS2PHrr",
"(V?)CVTSD2SSrr", "(V?)CVTSD2SSrr",
"(V?)CVTSI642SDrr", "(V?)CVTSI642SDrr",
"(V?)CVTSI2SDrr", "(V?)CVTSI2SDrr",
"(V?)CVTSI2SSrr", "(V?)CVTSI2SSrr",
"(V?)CVTTPD2DQrr")>; "(V?)CVT(T?)PD2DQrr")>;
def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 4; let Latency = 4;
@ -975,10 +964,9 @@ def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr", def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
"VCVTPD2DQYrr",
"VCVTPD2PSYrr", "VCVTPD2PSYrr",
"VCVTPS2PHYrr", "VCVTPS2PHYrr",
"VCVTTPD2DQYrr")>; "VCVT(T?)PD2DQYrr")>;
def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
let Latency = 6; let Latency = 6;
@ -1276,12 +1264,9 @@ def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm", def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
"(V?)CVTSD2SIrm", "(V?)CVT(T?)SD2SI64rm",
"(V?)CVTSS2SI64rm", "(V?)CVT(T?)SD2SIrm",
"(V?)CVTSS2SIrm",
"(V?)CVTTSD2SI64rm",
"(V?)CVTTSD2SIrm",
"VCVTTSS2SI64rm", "VCVTTSS2SI64rm",
"(V?)CVTTSS2SIrm")>; "(V?)CVTTSS2SIrm")>;
@ -1298,12 +1283,10 @@ def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>; def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm", def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm",
"CVTPD2PSrm", "CVT(T?)PD2DQrm",
"CVTTPD2DQrm",
"MMX_CVTPD2PIirm",
"MMX_CVTPI2PDirm", "MMX_CVTPI2PDirm",
"MMX_CVTTPD2PIirm", "MMX_CVT(T?)PD2PIirm",
"(V?)CVTDQ2PDrm", "(V?)CVTDQ2PDrm",
"(V?)CVTSD2SSrm")>; "(V?)CVTSD2SSrm")>;
@ -1350,10 +1333,8 @@ def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [2,1]; let ResourceCycles = [2,1];
} }
def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m", def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)16m",
"FICOM32m", "FICOM(P?)32m")>;
"FICOMP16m",
"FICOMP32m")>;
def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
let Latency = 10; let Latency = 10;

52
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -759,15 +759,11 @@ def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm",
"MOVNTI_64mr", "MOVNTI_64mr",
"MOVNTImr", "MOVNTImr",
"ST_FP(32|64|80)m", "ST_FP(32|64|80)m",
"(V?)MOVHPDmr", "(V?)MOV(H|L)(PD|PS)mr",
"(V?)MOVHPSmr",
"(V?)MOVLPDmr",
"(V?)MOVLPSmr",
"(V?)MOVPDI2DImr", "(V?)MOVPDI2DImr",
"(V?)MOVPQI2QImr", "(V?)MOVPQI2QImr",
"(V?)MOVPQIto64mr", "(V?)MOVPQIto64mr",
"(V?)MOVSDmr", "(V?)MOV(SD|SS)mr",
"(V?)MOVSSmr",
"VMPTRSTm")>; "VMPTRSTm")>;
def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
@ -1418,14 +1414,8 @@ def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVTSD2SI64rr", def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
"(V?)CVTSD2SIrr", "(V?)CVT(T?)SS2SI(64)?rr")>;
"(V?)CVTSS2SI64rr",
"(V?)CVTSS2SIrr",
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr",
"(V?)CVTTSS2SI64rr",
"(V?)CVTTSS2SIrr")>;
def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
let Latency = 4; let Latency = 4;
@ -1446,20 +1436,16 @@ def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPD2PIirr", def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr",
"MMX_CVTPI2PDirr", "MMX_CVT(T?)PD2PIirr",
"MMX_CVTPS2PIirr", "MMX_CVT(T?)PS2PIirr",
"MMX_CVTTPD2PIirr",
"MMX_CVTTPS2PIirr",
"(V?)CVTDQ2PDrr", "(V?)CVTDQ2PDrr",
"(V?)CVTPD2DQrr",
"(V?)CVTPD2PSrr", "(V?)CVTPD2PSrr",
"VCVTPS2PHrr", "VCVTPS2PHrr",
"(V?)CVTSD2SSrr", "(V?)CVTSD2SSrr",
"(V?)CVTSI642SDrr", "(V?)CVTSI(64)?2SDrr",
"(V?)CVTSI2SDrr",
"(V?)CVTSI2SSrr", "(V?)CVTSI2SSrr",
"(V?)CVTTPD2DQrr")>; "(V?)CVT(T?)PD2DQrr")>;
def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> { def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> {
let Latency = 4; let Latency = 4;
@ -1490,12 +1476,9 @@ def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI64rm", def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
"(V?)CVTSD2SIrm", "(V?)CVTSS2SI(64)?rm",
"(V?)CVTSS2SI64rm", "(V?)CVTTSD2SI(64)?rm",
"(V?)CVTSS2SIrm",
"(V?)CVTTSD2SI64rm",
"(V?)CVTTSD2SIrm",
"VCVTTSS2SI64rm", "VCVTTSS2SI64rm",
"(V?)CVTTSS2SIrm")>; "(V?)CVTTSS2SIrm")>;
@ -1511,11 +1494,9 @@ def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2DQrm", def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm",
"CVTPD2PSrm", "CVT(T?)PD2DQrm",
"CVTTPD2DQrm", "MMX_CVT(T?)PD2PIirm",
"MMX_CVTPD2PIirm",
"MMX_CVTTPD2PIirm",
"(V?)CVTDQ2PDrm")>; "(V?)CVTDQ2PDrm")>;
def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
@ -1682,10 +1663,9 @@ def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr", def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr",
"VCVTPD2DQYrr",
"VCVTPD2PSYrr", "VCVTPD2PSYrr",
"VCVTPS2PHYrr", "VCVTPS2PHYrr",
"VCVTTPD2DQYrr")>; "VCVT(T?)PD2DQYrr")>;
def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 13; let Latency = 13;

80
llvm/lib/Target/X86/X86SchedSandyBridge.td
View File

@ -705,16 +705,13 @@ def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr", def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr",
"MMX_CVTPI2PDirr", "MMX_CVT(T?)PD2PIirr",
"MMX_CVTTPD2PIirr",
"(V?)CVTDQ2PD(Y?)rr", "(V?)CVTDQ2PD(Y?)rr",
"(V?)CVTPD2DQ(Y?)rr",
"(V?)CVTPD2PS(Y?)rr", "(V?)CVTPD2PS(Y?)rr",
"(V?)CVTSD2SSrr", "(V?)CVTSD2SSrr",
"(V?)CVTSI642SDrr", "(V?)CVTSI(64)?2SDrr",
"(V?)CVTSI2SDrr", "(V?)CVT(T?)PD2DQ(Y?)rr")>;
"(V?)CVTTPD2DQ(Y?)rr")>;
def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let Latency = 4; let Latency = 4;
@ -761,14 +758,8 @@ def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVTSD2SI64rr", def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
"(V?)CVTSD2SIrr", "(V?)CVT(T?)SS2SI(64)?rr")>;
"(V?)CVTSS2SI64rr",
"(V?)CVTSS2SIrr",
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr",
"(V?)CVTTSS2SI64rr",
"(V?)CVTTSS2SIrr")>;
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 5; let Latency = 5;
@ -784,8 +775,7 @@ def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
let ResourceCycles = [1,2]; let ResourceCycles = [1,2];
} }
def: InstRW<[SBWriteResGroup35], (instregex "CLI")>; def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI642SSrr", def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI(64)?2SSrr")>;
"(V?)CVTSI2SSrr")>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5; let Latency = 5;
@ -1068,10 +1058,7 @@ def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SBWriteResGroup77], (instregex "(V?)COMISDrm", def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
"(V?)COMISSrm",
"(V?)UCOMISDrm",
"(V?)UCOMISSrm")>;
def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> { def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 8; let Latency = 8;
@ -1159,24 +1146,16 @@ def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm", def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVT(T?)PS2PIirm",
"MMX_CVTTPS2PIirm", "(V?)CVT(T?)PS2DQrm")>;
"(V?)CVTPS2DQrm",
"(V?)CVTTPS2DQrm")>;
def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 9; let Latency = 9;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm", def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm",
"CVTSD2SIrm", "CVT(T?)SS2SI(64)?rm")>;
"CVTSS2SI64rm",
"CVTSS2SIrm",
"CVTTSD2SI64rm",
"CVTTSD2SIrm",
"CVTTSS2SI64rm",
"CVTTSS2SIrm")>;
def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 9; let Latency = 9;
@ -1266,38 +1245,28 @@ def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m", "ILD_F(16|32|64)m",
"VCVTDQ2PSYrm", "VCVTDQ2PSYrm",
"VCVTPS2DQYrm", "VCVT(T?)PS2DQYrm")>;
"VCVTTPS2DQYrm")>;
def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 10; let Latency = 10;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm", def: InstRW<[SBWriteResGroup102], (instregex "VCVT(T?)SD2SI(64)?rm",
"VCVTSD2SIrm", "VCVT(T?)SS2SI(64)?rm")>;
"VCVTSS2SI64rm",
"VCVTSS2SIrm",
"VCVTTSD2SI64rm",
"VCVTTSD2SIrm",
"VCVTTSS2SI64rm",
"VCVTTSS2SIrm")>;
def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
let Latency = 10; let Latency = 10;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm", def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm",
"MMX_CVTPI2PDirm", "MMX_CVT(T?)PD2PIirm",
"MMX_CVTTPD2PIirm",
"(V?)CVTDQ2PD(Y?)rm", "(V?)CVTDQ2PD(Y?)rm",
"(V?)CVTPD2DQrm",
"(V?)CVTPD2PSrm", "(V?)CVTPD2PSrm",
"(V?)CVTSD2SSrm", "(V?)CVTSD2SSrm",
"(V?)CVTSI642SSrm", "(V?)CVTSI(64)?2SSrm",
"(V?)CVTSI2SSrm", "(V?)CVT(T?)PD2DQrm")>;
"(V?)CVTTPD2DQrm")>;
def SBWriteResGroup103_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { def SBWriteResGroup103_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 10; let Latency = 10;
@ -1319,19 +1288,16 @@ def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [2,1]; let ResourceCycles = [2,1];
} }
def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m", def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)16m",
"FICOM32m", "FICOM(P?)32m")>;
"FICOMP16m",
"FICOMP32m")>;
def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
let Latency = 11; let Latency = 11;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm", def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm",
"VCVTPD2PSYrm", "VCVT(T?)PD2DQYrm")>;
"VCVTTPD2DQYrm")>;
def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 12; let Latency = 12;

127
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -460,26 +460,15 @@ def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr", def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
"MMX_PADDSWirr", "MMX_PADDUS(B|W)irr",
"MMX_PADDUSBirr", "MMX_PAVG(B|W)irr",
"MMX_PADDUSWirr", "MMX_PCMPEQ(B|D|W)irr",
"MMX_PAVGBirr", "MMX_PCMPGT(B|D|W)irr",
"MMX_PAVGWirr", "MMX_P(MAX|MIN)SWirr",
"MMX_PCMPEQBirr", "MMX_P(MAX|MIN)UBirr",
"MMX_PCMPEQDirr", "MMX_PSUBS(B|W)irr",
"MMX_PCMPEQWirr", "MMX_PSUBUS(B|W)irr")>;
"MMX_PCMPGTBirr",
"MMX_PCMPGTDirr",
"MMX_PCMPGTWirr",
"MMX_PMAXSWirr",
"MMX_PMAXUBirr",
"MMX_PMINSWirr",
"MMX_PMINUBirr",
"MMX_PSUBSBirr",
"MMX_PSUBSWirr",
"MMX_PSUBUSBirr",
"MMX_PSUBUSWirr")>;
def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
let Latency = 1; let Latency = 1;
@ -556,15 +545,9 @@ def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADDB(Y?)rr", def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
"(V?)PADDD(Y?)rr",
"(V?)PADDQ(Y?)rr",
"(V?)PADDW(Y?)rr",
"VPBLENDD(Y?)rri", "VPBLENDD(Y?)rri",
"(V?)PSUBB(Y?)rr", "(V?)PSUB(B|D|Q|W)(Y?)rr")>;
"(V?)PSUBD(Y?)rr",
"(V?)PSUBQ(Y?)rr",
"(V?)PSUBW(Y?)rr")>;
def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let Latency = 1; let Latency = 1;
@ -596,15 +579,11 @@ def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
"MOVNTI_64mr", "MOVNTI_64mr",
"MOVNTImr", "MOVNTImr",
"ST_FP(32|64|80)m", "ST_FP(32|64|80)m",
"(V?)MOVHPDmr", "(V?)MOV(H|L)(PD|PS)mr",
"(V?)MOVHPSmr",
"(V?)MOVLPDmr",
"(V?)MOVLPSmr",
"(V?)MOVPDI2DImr", "(V?)MOVPDI2DImr",
"(V?)MOVPQI2QImr", "(V?)MOVPQI2QImr",
"(V?)MOVPQIto64mr", "(V?)MOVPQIto64mr",
"(V?)MOVSDmr", "(V?)MOV(SD|SS)mr",
"(V?)MOVSSmr",
"VMPTRSTm")>; "VMPTRSTm")>;
def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> { def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
@ -872,8 +851,7 @@ def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr", "(V?)CVT(T?)PS2DQ(Y?)rr")>;
"(V?)CVTTPS2DQ(Y?)rr")>;
def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
let Latency = 4; let Latency = 4;
@ -950,11 +928,9 @@ def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr", def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
"MMX_CVTPS2PIirr", "MMX_CVT(T?)PS2PIirr",
"MMX_CVTTPD2PIirr", "(V?)CVT(T?)PD2DQrr",
"MMX_CVTTPS2PIirr",
"(V?)CVTPD2DQrr",
"(V?)CVTPD2PSrr", "(V?)CVTPD2PSrr",
"VCVTPH2PSrr", "VCVTPH2PSrr",
"(V?)CVTPS2PDrr", "(V?)CVTPS2PDrr",
@ -963,8 +939,7 @@ def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr",
"(V?)CVTSI642SDrr", "(V?)CVTSI642SDrr",
"(V?)CVTSI2SDrr", "(V?)CVTSI2SDrr",
"(V?)CVTSI2SSrr", "(V?)CVTSI2SSrr",
"(V?)CVTSS2SDrr", "(V?)CVTSS2SDrr")>;
"(V?)CVTTPD2DQrr")>;
def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
let Latency = 5; let Latency = 5;
@ -1051,12 +1026,8 @@ def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSD2SI64rr", def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
"(V?)CVTSD2SIrr", "(V?)CVT(T?)SD2SI(64)?rr")>;
"(V?)CVTSS2SI64rr",
"(V?)CVTSS2SIrr",
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr")>;
def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6; let Latency = 6;
@ -1229,12 +1200,11 @@ def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr", def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr",
"VCVTPD2PSYrr",
"VCVTPH2PSYrr", "VCVTPH2PSYrr",
"VCVTPS2PDYrr", "VCVTPS2PDYrr",
"VCVTPS2PHYrr", "VCVTPS2PHYrr",
"VCVTTPD2DQYrr")>; "VCVT(T?)PD2DQYrr")>;
def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 7; let Latency = 7;
@ -1243,15 +1213,9 @@ def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
} }
def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm", def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm",
"(V?)INSERTI128rm", "(V?)INSERTI128rm",
"(V?)PADDBrm", "(V?)PADD(B|D|Q|W)rm",
"(V?)PADDDrm",
"(V?)PADDQrm",
"(V?)PADDWrm",
"(V?)PBLENDDrmi", "(V?)PBLENDDrmi",
"(V?)PSUBBrm", "(V?)PSUB(B|D|Q|W)rm")>;
"(V?)PSUBDrm",
"(V?)PSUBQrm",
"(V?)PSUBWrm")>;
def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 7; let Latency = 7;
@ -1282,8 +1246,7 @@ def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI64rr", def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
"(V?)CVTTSS2SIrr")>;
def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
let Latency = 7; let Latency = 7;
@ -1375,15 +1338,9 @@ def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup110], (instregex "VPADDBYrm", def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm",
"VPADDDYrm",
"VPADDQYrm",
"VPADDWYrm",
"VPBLENDDYrmi", "VPBLENDDYrmi",
"VPSUBBYrm", "VPSUB(B|D|Q|W)Yrm")>;
"VPSUBDYrm",
"VPSUBQYrm",
"VPSUBWYrm")>;
def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 8; let Latency = 8;
@ -1467,8 +1424,7 @@ def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let NumMicroOps = 2; let NumMicroOps = 2;
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTPS2PIirm", def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
"MMX_CVTTPS2PIirm",
"VCVTPH2PSrm", "VCVTPH2PSrm",
"(V?)CVTPS2PDrm")>; "(V?)CVTPS2PDrm")>;
@ -1579,19 +1535,16 @@ def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
let ResourceCycles = [1,1]; let ResourceCycles = [1,1];
} }
def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm", def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm",
"VCVTPS2DQYrm",
"VCVTPS2PDYrm", "VCVTPS2PDYrm",
"VCVTTPS2DQYrm")>; "VCVT(T?)PS2DQYrm")>;
def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 11; let Latency = 11;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [2,1]; let ResourceCycles = [2,1];
} }
def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m", def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)16m",
"FICOM32m", "FICOM(P?)32m")>;
"FICOMP16m",
"FICOMP32m")>;
def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 11; let Latency = 11;
@ -1605,25 +1558,19 @@ def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSD2SI64rm", def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
"(V?)CVTSD2SIrm", "(V?)CVT(T?)SD2SI(64)?rm",
"(V?)CVTSS2SI64rm",
"(V?)CVTSS2SIrm",
"(V?)CVTTSD2SI64rm",
"(V?)CVTTSD2SIrm",
"VCVTTSS2SI64rm", "VCVTTSS2SI64rm",
"(V?)CVTTSS2SIrm")>; "(V?)CVT(T?)SS2SIrm")>;
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 11; let Latency = 11;
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm", def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm",
"CVTPD2PSrm", "CVT(T?)PD2DQrm",
"CVTTPD2DQrm", "MMX_CVT(T?)PD2PIirm")>;
"MMX_CVTPD2PIirm",
"MMX_CVTTPD2PIirm")>;
def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 11; let Latency = 11;

1101
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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