From d5d4cdb49de21011b847ea7c5a819c03caeec965 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 9 May 2018 19:04:15 +0000 Subject: [PATCH] [X86] Merge instregex patterns to reduce InstrRW compile time. llvm-svn: 331911 --- llvm/lib/Target/X86/X86SchedBroadwell.td | 57 +- llvm/lib/Target/X86/X86SchedHaswell.td | 52 +- llvm/lib/Target/X86/X86SchedSandyBridge.td | 80 +- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 127 +- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 1101 +++++------------- 5 files changed, 365 insertions(+), 1052 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 3fa70f1023f6..f97bd3df1f6b 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -566,15 +566,11 @@ def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm", "MOVNTI_64mr", "MOVNTImr", "ST_FP(32|64|80)m", - "(V?)MOVHPDmr", - "(V?)MOVHPSmr", - "(V?)MOVLPDmr", - "(V?)MOVLPSmr", + "(V?)MOV(H|L)(PD|PS)mr", "(V?)MOVPDI2DImr", "(V?)MOVPQI2QImr", "(V?)MOVPQIto64mr", - "(V?)MOVSDmr", - "(V?)MOVSSmr")>; + "(V?)MOV(SD|SS)mr")>; def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { let Latency = 2; @@ -778,14 +774,10 @@ def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr", - "(V?)CVTSD2SIrr", - "(V?)CVTSS2SI64rr", - "(V?)CVTSS2SIrr", - "(V?)CVTTSD2SI64rr", - "(V?)CVTTSD2SIrr", - "(V?)CVTTSS2SI64rr", - "(V?)CVTTSS2SIrr")>; +def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr", + "(V?)CVT(T?)SD2SIrr", + "(V?)CVT(T?)SS2SI64rr", + "(V?)CVT(T?)SS2SIrr")>; def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { let Latency = 4; @@ -807,20 +799,17 @@ def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { let ResourceCycles = [1,1]; } def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>; -def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr", - "MMX_CVTPI2PDirr", - "MMX_CVTPS2PIirr", - "MMX_CVTTPD2PIirr", - "MMX_CVTTPS2PIirr", +def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", "(V?)CVTDQ2PDrr", - "(V?)CVTPD2DQrr", "(V?)CVTPD2PSrr", "VCVTPS2PHrr", "(V?)CVTSD2SSrr", "(V?)CVTSI642SDrr", "(V?)CVTSI2SDrr", "(V?)CVTSI2SSrr", - "(V?)CVTTPD2DQrr")>; + "(V?)CVT(T?)PD2DQrr")>; def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { let Latency = 4; @@ -975,10 +964,9 @@ def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> { let ResourceCycles = [1,1]; } def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr", - "VCVTPD2DQYrr", "VCVTPD2PSYrr", "VCVTPS2PHYrr", - "VCVTTPD2DQYrr")>; + "VCVT(T?)PD2DQYrr")>; def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { let Latency = 6; @@ -1276,12 +1264,9 @@ def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm", - "(V?)CVTSD2SIrm", - "(V?)CVTSS2SI64rm", - "(V?)CVTSS2SIrm", - "(V?)CVTTSD2SI64rm", - "(V?)CVTTSD2SIrm", +def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm", + "(V?)CVT(T?)SD2SI64rm", + "(V?)CVT(T?)SD2SIrm", "VCVTTSS2SI64rm", "(V?)CVTTSS2SIrm")>; @@ -1298,12 +1283,10 @@ def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { let ResourceCycles = [1,1,1]; } def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>; -def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm", - "CVTPD2PSrm", - "CVTTPD2DQrm", - "MMX_CVTPD2PIirm", +def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", "MMX_CVTPI2PDirm", - "MMX_CVTTPD2PIirm", + "MMX_CVT(T?)PD2PIirm", "(V?)CVTDQ2PDrm", "(V?)CVTSD2SSrm")>; @@ -1350,10 +1333,8 @@ def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m", - "FICOM32m", - "FICOMP16m", - "FICOMP32m")>; +def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)16m", + "FICOM(P?)32m")>; def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { let Latency = 10; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index aef283af51ae..1e431e078cd9 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -759,15 +759,11 @@ def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm", "MOVNTI_64mr", "MOVNTImr", "ST_FP(32|64|80)m", - "(V?)MOVHPDmr", - "(V?)MOVHPSmr", - "(V?)MOVLPDmr", - "(V?)MOVLPSmr", + "(V?)MOV(H|L)(PD|PS)mr", "(V?)MOVPDI2DImr", "(V?)MOVPQI2QImr", "(V?)MOVPQIto64mr", - "(V?)MOVSDmr", - "(V?)MOVSSmr", + "(V?)MOV(SD|SS)mr", "VMPTRSTm")>; def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { @@ -1418,14 +1414,8 @@ def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVTSD2SI64rr", - "(V?)CVTSD2SIrr", - "(V?)CVTSS2SI64rr", - "(V?)CVTSS2SIrr", - "(V?)CVTTSD2SI64rr", - "(V?)CVTTSD2SIrr", - "(V?)CVTTSS2SI64rr", - "(V?)CVTTSS2SIrr")>; +def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", + "(V?)CVT(T?)SS2SI(64)?rr")>; def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { let Latency = 4; @@ -1446,20 +1436,16 @@ def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPD2PIirr", - "MMX_CVTPI2PDirr", - "MMX_CVTPS2PIirr", - "MMX_CVTTPD2PIirr", - "MMX_CVTTPS2PIirr", +def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", "(V?)CVTDQ2PDrr", - "(V?)CVTPD2DQrr", "(V?)CVTPD2PSrr", "VCVTPS2PHrr", "(V?)CVTSD2SSrr", - "(V?)CVTSI642SDrr", - "(V?)CVTSI2SDrr", + "(V?)CVTSI(64)?2SDrr", "(V?)CVTSI2SSrr", - "(V?)CVTTPD2DQrr")>; + "(V?)CVT(T?)PD2DQrr")>; def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> { let Latency = 4; @@ -1490,12 +1476,9 @@ def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI64rm", - "(V?)CVTSD2SIrm", - "(V?)CVTSS2SI64rm", - "(V?)CVTSS2SIrm", - "(V?)CVTTSD2SI64rm", - "(V?)CVTTSD2SIrm", +def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", + "(V?)CVTSS2SI(64)?rm", + "(V?)CVTTSD2SI(64)?rm", "VCVTTSS2SI64rm", "(V?)CVTTSS2SIrm")>; @@ -1511,11 +1494,9 @@ def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2DQrm", - "CVTPD2PSrm", - "CVTTPD2DQrm", - "MMX_CVTPD2PIirm", - "MMX_CVTTPD2PIirm", +def: InstRW<[HWWriteResGroup78], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm", "(V?)CVTDQ2PDrm")>; def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { @@ -1682,10 +1663,9 @@ def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { let ResourceCycles = [1,1]; } def: InstRW<[HWWriteResGroup102], (instregex "VCVTDQ2PDYrr", - "VCVTPD2DQYrr", "VCVTPD2PSYrr", "VCVTPS2PHYrr", - "VCVTTPD2DQYrr")>; + "VCVT(T?)PD2DQYrr")>; def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { let Latency = 13; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 41f6d10a849f..295c724b6397 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -705,16 +705,13 @@ def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr", - "MMX_CVTPI2PDirr", - "MMX_CVTTPD2PIirr", +def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr", + "MMX_CVT(T?)PD2PIirr", "(V?)CVTDQ2PD(Y?)rr", - "(V?)CVTPD2DQ(Y?)rr", "(V?)CVTPD2PS(Y?)rr", "(V?)CVTSD2SSrr", - "(V?)CVTSI642SDrr", - "(V?)CVTSI2SDrr", - "(V?)CVTTPD2DQ(Y?)rr")>; + "(V?)CVTSI(64)?2SDrr", + "(V?)CVT(T?)PD2DQ(Y?)rr")>; def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { let Latency = 4; @@ -761,14 +758,8 @@ def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVTSD2SI64rr", - "(V?)CVTSD2SIrr", - "(V?)CVTSS2SI64rr", - "(V?)CVTSS2SIrr", - "(V?)CVTTSD2SI64rr", - "(V?)CVTTSD2SIrr", - "(V?)CVTTSS2SI64rr", - "(V?)CVTTSS2SIrr")>; +def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVT(T?)SD2SI(64)?rr", + "(V?)CVT(T?)SS2SI(64)?rr")>; def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { let Latency = 5; @@ -784,8 +775,7 @@ def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { let ResourceCycles = [1,2]; } def: InstRW<[SBWriteResGroup35], (instregex "CLI")>; -def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI642SSrr", - "(V?)CVTSI2SSrr")>; +def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI(64)?2SSrr")>; def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { let Latency = 5; @@ -1068,10 +1058,7 @@ def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup77], (instregex "(V?)COMISDrm", - "(V?)COMISSrm", - "(V?)UCOMISDrm", - "(V?)UCOMISSrm")>; +def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> { let Latency = 8; @@ -1159,24 +1146,16 @@ def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm", - "MMX_CVTTPS2PIirm", - "(V?)CVTPS2DQrm", - "(V?)CVTTPS2DQrm")>; +def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVT(T?)PS2PIirm", + "(V?)CVT(T?)PS2DQrm")>; def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let Latency = 9; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm", - "CVTSD2SIrm", - "CVTSS2SI64rm", - "CVTSS2SIrm", - "CVTTSD2SI64rm", - "CVTTSD2SIrm", - "CVTTSS2SI64rm", - "CVTTSS2SIrm")>; +def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm", + "CVT(T?)SS2SI(64)?rm")>; def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let Latency = 9; @@ -1266,38 +1245,28 @@ def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", "ILD_F(16|32|64)m", "VCVTDQ2PSYrm", - "VCVTPS2DQYrm", - "VCVTTPS2DQYrm")>; + "VCVT(T?)PS2DQYrm")>; def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let Latency = 10; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm", - "VCVTSD2SIrm", - "VCVTSS2SI64rm", - "VCVTSS2SIrm", - "VCVTTSD2SI64rm", - "VCVTTSD2SIrm", - "VCVTTSS2SI64rm", - "VCVTTSS2SIrm")>; +def: InstRW<[SBWriteResGroup102], (instregex "VCVT(T?)SD2SI(64)?rm", + "VCVT(T?)SS2SI(64)?rm")>; def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { let Latency = 10; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm", - "MMX_CVTPI2PDirm", - "MMX_CVTTPD2PIirm", +def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm", + "MMX_CVT(T?)PD2PIirm", "(V?)CVTDQ2PD(Y?)rm", - "(V?)CVTPD2DQrm", "(V?)CVTPD2PSrm", "(V?)CVTSD2SSrm", - "(V?)CVTSI642SSrm", - "(V?)CVTSI2SSrm", - "(V?)CVTTPD2DQrm")>; + "(V?)CVTSI(64)?2SSrm", + "(V?)CVT(T?)PD2DQrm")>; def SBWriteResGroup103_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { let Latency = 10; @@ -1319,19 +1288,16 @@ def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m", - "FICOM32m", - "FICOMP16m", - "FICOMP32m")>; +def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)16m", + "FICOM(P?)32m")>; def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { let Latency = 11; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm", - "VCVTPD2PSYrm", - "VCVTTPD2DQYrm")>; +def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm", + "VCVT(T?)PD2DQYrm")>; def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { let Latency = 12; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 84b0055be38e..d521864f6dbf 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -460,26 +460,15 @@ def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr", - "MMX_PADDSWirr", - "MMX_PADDUSBirr", - "MMX_PADDUSWirr", - "MMX_PAVGBirr", - "MMX_PAVGWirr", - "MMX_PCMPEQBirr", - "MMX_PCMPEQDirr", - "MMX_PCMPEQWirr", - "MMX_PCMPGTBirr", - "MMX_PCMPGTDirr", - "MMX_PCMPGTWirr", - "MMX_PMAXSWirr", - "MMX_PMAXUBirr", - "MMX_PMINSWirr", - "MMX_PMINUBirr", - "MMX_PSUBSBirr", - "MMX_PSUBSWirr", - "MMX_PSUBUSBirr", - "MMX_PSUBUSWirr")>; +def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr")>; def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { let Latency = 1; @@ -556,15 +545,9 @@ def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADDB(Y?)rr", - "(V?)PADDD(Y?)rr", - "(V?)PADDQ(Y?)rr", - "(V?)PADDW(Y?)rr", +def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", "VPBLENDD(Y?)rri", - "(V?)PSUBB(Y?)rr", - "(V?)PSUBD(Y?)rr", - "(V?)PSUBQ(Y?)rr", - "(V?)PSUBW(Y?)rr")>; + "(V?)PSUB(B|D|Q|W)(Y?)rr")>; def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { let Latency = 1; @@ -596,15 +579,11 @@ def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm", "MOVNTI_64mr", "MOVNTImr", "ST_FP(32|64|80)m", - "(V?)MOVHPDmr", - "(V?)MOVHPSmr", - "(V?)MOVLPDmr", - "(V?)MOVLPSmr", + "(V?)MOV(H|L)(PD|PS)mr", "(V?)MOVPDI2DImr", "(V?)MOVPQI2QImr", "(V?)MOVPQIto64mr", - "(V?)MOVSDmr", - "(V?)MOVSSmr", + "(V?)MOV(SD|SS)mr", "VMPTRSTm")>; def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> { @@ -872,8 +851,7 @@ def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { let ResourceCycles = [1]; } def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", - "(V?)CVTPS2DQ(Y?)rr", - "(V?)CVTTPS2DQ(Y?)rr")>; + "(V?)CVT(T?)PS2DQ(Y?)rr")>; def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { let Latency = 4; @@ -950,11 +928,9 @@ def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr", - "MMX_CVTPS2PIirr", - "MMX_CVTTPD2PIirr", - "MMX_CVTTPS2PIirr", - "(V?)CVTPD2DQrr", +def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", + "(V?)CVT(T?)PD2DQrr", "(V?)CVTPD2PSrr", "VCVTPH2PSrr", "(V?)CVTPS2PDrr", @@ -963,8 +939,7 @@ def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr", "(V?)CVTSI642SDrr", "(V?)CVTSI2SDrr", "(V?)CVTSI2SSrr", - "(V?)CVTSS2SDrr", - "(V?)CVTTPD2DQrr")>; + "(V?)CVTSS2SDrr")>; def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { let Latency = 5; @@ -1051,12 +1026,8 @@ def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSD2SI64rr", - "(V?)CVTSD2SIrr", - "(V?)CVTSS2SI64rr", - "(V?)CVTSS2SIrr", - "(V?)CVTTSD2SI64rr", - "(V?)CVTTSD2SIrr")>; +def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", + "(V?)CVT(T?)SD2SI(64)?rr")>; def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { let Latency = 6; @@ -1229,12 +1200,11 @@ def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr", - "VCVTPD2PSYrr", +def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr", "VCVTPH2PSYrr", "VCVTPS2PDYrr", "VCVTPS2PHYrr", - "VCVTTPD2DQYrr")>; + "VCVT(T?)PD2DQYrr")>; def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { let Latency = 7; @@ -1243,15 +1213,9 @@ def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { } def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm", "(V?)INSERTI128rm", - "(V?)PADDBrm", - "(V?)PADDDrm", - "(V?)PADDQrm", - "(V?)PADDWrm", + "(V?)PADD(B|D|Q|W)rm", "(V?)PBLENDDrmi", - "(V?)PSUBBrm", - "(V?)PSUBDrm", - "(V?)PSUBQrm", - "(V?)PSUBWrm")>; + "(V?)PSUB(B|D|Q|W)rm")>; def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { let Latency = 7; @@ -1282,8 +1246,7 @@ def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI64rr", - "(V?)CVTTSS2SIrr")>; +def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { let Latency = 7; @@ -1375,15 +1338,9 @@ def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup110], (instregex "VPADDBYrm", - "VPADDDYrm", - "VPADDQYrm", - "VPADDWYrm", +def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm", "VPBLENDDYrmi", - "VPSUBBYrm", - "VPSUBDYrm", - "VPSUBQYrm", - "VPSUBWYrm")>; + "VPSUB(B|D|Q|W)Yrm")>; def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { let Latency = 8; @@ -1467,8 +1424,7 @@ def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTPS2PIirm", - "MMX_CVTTPS2PIirm", +def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", "VCVTPH2PSrm", "(V?)CVTPS2PDrm")>; @@ -1579,19 +1535,16 @@ def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { let ResourceCycles = [1,1]; } def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm", - "VCVTPS2DQYrm", "VCVTPS2PDYrm", - "VCVTTPS2DQYrm")>; + "VCVT(T?)PS2DQYrm")>; def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { let Latency = 11; let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m", - "FICOM32m", - "FICOMP16m", - "FICOMP32m")>; +def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)16m", + "FICOM(P?)32m")>; def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { let Latency = 11; @@ -1605,25 +1558,19 @@ def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSD2SI64rm", - "(V?)CVTSD2SIrm", - "(V?)CVTSS2SI64rm", - "(V?)CVTSS2SIrm", - "(V?)CVTTSD2SI64rm", - "(V?)CVTTSD2SIrm", +def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", + "(V?)CVT(T?)SD2SI(64)?rm", "VCVTTSS2SI64rm", - "(V?)CVTTSS2SIrm")>; + "(V?)CVT(T?)SS2SIrm")>; def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { let Latency = 11; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm", - "CVTPD2PSrm", - "CVTTPD2DQrm", - "MMX_CVTPD2PIirm", - "MMX_CVTTPD2PIirm")>; +def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { let Latency = 11; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 76755c6ad3a9..3f0b51d140dc 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -460,66 +460,26 @@ def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup1], (instregex "KANDBrr", - "KANDDrr", - "KANDNBrr", - "KANDNDrr", - "KANDNQrr", - "KANDNWrr", - "KANDQrr", - "KANDWrr", - "KMOVBkk", - "KMOVDkk", - "KMOVQkk", - "KMOVWkk", - "KNOTBrr", - "KNOTDrr", - "KNOTQrr", - "KNOTWrr", - "KORBrr", - "KORDrr", - "KORQrr", - "KORWrr", - "KXNORBrr", - "KXNORDrr", - "KXNORQrr", - "KXNORWrr", - "KXORBrr", - "KXORDrr", - "KXORQrr", - "KXORWrr", - "MMX_PADDSBirr", - "MMX_PADDSWirr", - "MMX_PADDUSBirr", - "MMX_PADDUSWirr", - "MMX_PAVGBirr", - "MMX_PAVGWirr", - "MMX_PCMPEQBirr", - "MMX_PCMPEQDirr", - "MMX_PCMPEQWirr", - "MMX_PCMPGTBirr", - "MMX_PCMPGTDirr", - "MMX_PCMPGTWirr", - "MMX_PMAXSWirr", - "MMX_PMAXUBirr", - "MMX_PMINSWirr", - "MMX_PMINUBirr", - "MMX_PSUBSBirr", - "MMX_PSUBSWirr", - "MMX_PSUBUSBirr", - "MMX_PSUBUSWirr", - "VPMOVB2MZ128rr", - "VPMOVB2MZ256rr", - "VPMOVB2MZrr", - "VPMOVD2MZ128rr", - "VPMOVD2MZ256rr", - "VPMOVD2MZrr", - "VPMOVQ2MZ128rr", - "VPMOVQ2MZ256rr", - "VPMOVQ2MZrr", - "VPMOVW2MZ128rr", - "VPMOVW2MZ256rr", - "VPMOVW2MZrr")>; +def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", + "KANDN(B|D|Q|W)rr", + "KMOV(B|D|Q|W)kk", + "KNOT(B|D|Q|W)rr", + "KOR(B|D|Q|W)rr", + "KXNOR(B|D|Q|W)rr", + "KXOR(B|D|Q|W)rr", + "MMX_PADDS(B|W)irr", + "MMX_PADDUS(B|W)irr", + "MMX_PAVG(B|W)irr", + "MMX_PCMPEQ(B|D|W)irr", + "MMX_PCMPGT(B|D|W)irr", + "MMX_P(MAX|MIN)SWirr", + "MMX_P(MAX|MIN)UBirr", + "MMX_PSUBS(B|W)irr", + "MMX_PSUBUS(B|W)irr", + "VPMOVB2M(Z|Z128|Z256)rr", + "VPMOVD2M(Z|Z128|Z256)rr", + "VPMOVQ2M(Z|Z128|Z256)rr", + "VPMOVW2M(Z|Z128|Z256)rr")>; def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { let Latency = 1; @@ -528,20 +488,15 @@ def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { } def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r", "COM_FST0r", - "KMOVBkr", - "KMOVDkr", - "KMOVQkr", - "KMOVWkr", + "KMOV(B|D|Q|W)kr", "MMX_MOVD64rr", "MMX_MOVD64to64rr", "MOV64toPQIrr", "MOVDI2PDIrr", "UCOM_FPr", "UCOM_Fr", - "VMOV64toPQIZrr", - "VMOV64toPQIrr", - "VMOVDI2PDIZrr", - "VMOVDI2PDIrr")>; + "VMOV64toPQI(Z?)rr", + "VMOVDI2PDI(Z?)rr")>; def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { let Latency = 1; @@ -604,71 +559,19 @@ def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPDZ128rr", - "VBLENDMPDZ256rr", - "VBLENDMPDZrr", - "VBLENDMPSZ128rr", - "VBLENDMPSZ256rr", - "VBLENDMPSZrr", - "VPADDBYrr", - "VPADDBZ128rr", - "VPADDBZ256rr", - "VPADDBZrr", - "(V?)PADDBrr", - "VPADDDYrr", - "VPADDDZ128rr", - "VPADDDZ256rr", - "VPADDDZrr", - "(V?)PADDDrr", - "VPADDQYrr", - "VPADDQZ128rr", - "VPADDQZ256rr", - "VPADDQZrr", - "(V?)PADDQrr", - "VPADDWYrr", - "VPADDWZ128rr", - "VPADDWZ256rr", - "VPADDWZrr", - "(V?)PADDWrr", - "VPBLENDDYrri", - "VPBLENDDrri", - "VPBLENDMBZ128rr", - "VPBLENDMBZ256rr", - "VPBLENDMBZrr", - "VPBLENDMDZ128rr", - "VPBLENDMDZ256rr", - "VPBLENDMDZrr", - "VPBLENDMQZ128rr", - "VPBLENDMQZ256rr", - "VPBLENDMQZrr", - "VPBLENDMWZ128rr", - "VPBLENDMWZ256rr", - "VPBLENDMWZrr", - "VPSUBBYrr", - "VPSUBBZ128rr", - "VPSUBBZ256rr", - "VPSUBBZrr", - "(V?)PSUBBrr", - "VPSUBDYrr", - "VPSUBDZ128rr", - "VPSUBDZ256rr", - "VPSUBDZrr", - "(V?)PSUBDrr", - "VPSUBQYrr", - "VPSUBQZ128rr", - "VPSUBQZ256rr", - "VPSUBQZrr", - "(V?)PSUBQrr", - "VPSUBWYrr", - "VPSUBWZ128rr", - "VPSUBWZrr", - "(V?)PSUBWrr", - "VPTERNLOGDZ128rri", - "VPTERNLOGDZ256rri", - "VPTERNLOGDZrri", - "VPTERNLOGQZ128rri", - "VPTERNLOGQZ256rri", - "VPTERNLOGQZrri")>; +def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z|Z128|Z256)rr", + "VBLENDMPS(Z|Z128|Z256)rr", + "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PADD(B|D|Q|W)rr", + "VPBLENDD(Y?)rri", + "VPBLENDMB(Z|Z128|Z256)rr", + "VPBLENDMD(Z|Z128|Z256)rr", + "VPBLENDMQ(Z|Z128|Z256)rr", + "VPBLENDMW(Z|Z128|Z256)rr", + "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr", + "(V?)PSUB(B|D|Q|W)rr", + "VPTERNLOGD(Z|Z128|Z256)rri", + "VPTERNLOGQ(Z|Z128|Z256)rri")>; def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { let Latency = 1; @@ -693,46 +596,26 @@ def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { let ResourceCycles = [1,1]; } def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm", - "KMOVBmk", - "KMOVDmk", - "KMOVQmk", - "KMOVWmk", + "KMOV(B|D|Q|W)mk", "MMX_MOVD64from64rm", "MMX_MOVD64mr", "MMX_MOVNTQmr", "MMX_MOVQ64mr", - "MOVHPDmr", - "MOVHPSmr", - "MOVLPDmr", - "MOVLPSmr", "MOVNTDQmr", "MOVNTI_64mr", "MOVNTImr", - "MOVPDI2DImr", - "MOVPQI2QImr", - "MOVPQIto64mr", - "MOVSDmr", - "MOVSSmr", "ST_FP32m", "ST_FP64m", "ST_FP80m", - "VMOVHPDZ128mr(b?)", - "VMOVHPDmr", - "VMOVHPSZ128mr(b?)", - "VMOVHPSmr", - "VMOVLPDZ128mr(b?)", - "VMOVLPDmr", - "VMOVLPSZ128mr(b?)", - "VMOVLPSmr", + "VMOV(H|L)(PD|PS)Z128mr(b?)", + "(V?)MOV(H|L)(PD|PS)mr", "VMOVPDI2DIZmr(b?)", - "VMOVPDI2DImr", + "(V?)MOVPDI2DImr", "VMOVPQI(2QI|to64)Zmr(b?)", - "VMOVPQI2QImr", - "VMOVPQIto64mr", - "VMOVSDZmr(b?)", - "VMOVSDmr", - "VMOVSSZmr(b?)", - "VMOVSSmr", + "(V?)MOVPQI2QImr", + "(V?)MOVPQIto64mr", + "VMOV(SD|SS)Zmr(b?)", + "(V?)MOV(SD|SS)mr", "VMPTRSTm")>; def SKXWriteResGroup12 : SchedWriteRes<[SKXPort0]> { @@ -861,22 +744,10 @@ def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup30], (instregex "KADDBrr", - "KADDDrr", - "KADDQrr", - "KADDWrr", - "KMOVBrk", - "KMOVDrk", - "KMOVQrk", - "KMOVWrk", - "KORTESTBrr", - "KORTESTDrr", - "KORTESTQrr", - "KORTESTWrr", - "KTESTBrr", - "KTESTDrr", - "KTESTQrr", - "KTESTWrr")>; +def: InstRW<[SKXWriteResGroup30], (instregex "KADD(B|D|Q|W)rr", + "KMOV(B|D|Q|W)rk", + "KORTEST(B|D|Q|W)rr", + "KTEST(B|D|Q|W)rr")>; def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { let Latency = 3; @@ -905,129 +776,35 @@ def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_FPrST0", "(ADD|SUB|SUBR)_FST0r", "(ADD|SUB|SUBR)_FrST0", - "KSHIFTLBri", - "KSHIFTLDri", - "KSHIFTLQri", - "KSHIFTLWri", - "KSHIFTRBri", - "KSHIFTRDri", - "KSHIFTRQri", - "KSHIFTRWri", + "KSHIFTL(B|D|Q|W)ri", + "KSHIFTR(B|D|Q|W)ri", "KUNPCKBWrr", "KUNPCKDQrr", "KUNPCKWDrr", - "VALIGNDZ128rri", - "VALIGNDZ256rri", - "VALIGNDZrri", - "VALIGNQZ128rri", - "VALIGNQZ256rri", - "VALIGNQZrri", - "VCMPPDZ128rri", - "VCMPPDZ256rri", - "VCMPPDZrri", - "VCMPPSZ128rri", - "VCMPPSZ256rri", - "VCMPPSZrri", + "VALIGND(Z|Z128|Z256)rri", + "VALIGNQ(Z|Z128|Z256)rri", + "VCMPPD(Z|Z128|Z256)rri", + "VCMPPS(Z|Z128|Z256)rri", "VCMPSDZrr", "VCMPSSZrr", "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. - "VFPCLASSPDZ128rr", - "VFPCLASSPDZ256rr", - "VFPCLASSPDZrr", - "VFPCLASSPSZ128rr", - "VFPCLASSPSZ256rr", - "VFPCLASSPSZrr", + "VFPCLASSPD(Z|Z128|Z256)rr", + "VFPCLASSPS(Z|Z128|Z256)rr", "VFPCLASSSDrr", "VFPCLASSSSrr", "VPBROADCASTBrr", "VPBROADCASTWrr", - "VPCMPBZ128rri", - "VPCMPBZ256rri", - "VPCMPBZrri", - "VPCMPDZ128rri", - "VPCMPDZ256rri", - "VPCMPDZrri", - "VPCMPEQBZ128rr", - "VPCMPEQBZ256rr", - "VPCMPEQBZrr", - "VPCMPEQDZ128rr", - "VPCMPEQDZ256rr", - "VPCMPEQDZrr", - "VPCMPEQQZ128rr", - "VPCMPEQQZ256rr", - "VPCMPEQQZrr", - "VPCMPEQWZ128rr", - "VPCMPEQWZ256rr", - "VPCMPEQWZrr", - "VPCMPGTBZ128rr", - "VPCMPGTBZ256rr", - "VPCMPGTBZrr", - "VPCMPGTDZ128rr", - "VPCMPGTDZ256rr", - "VPCMPGTDZrr", - "VPCMPGTQYrr", - "VPCMPGTQZ128rr", - "VPCMPGTQZ256rr", - "VPCMPGTQZrr", - "(V?)PCMPGTQrr", - "VPCMPGTWZ128rr", - "VPCMPGTWZ256rr", - "VPCMPGTWZrr", - "VPCMPQZ128rri", - "VPCMPQZ256rri", - "VPCMPQZrri", - "VPCMPUBZ128rri", - "VPCMPUBZ256rri", - "VPCMPUBZrri", - "VPCMPUDZ128rri", - "VPCMPUDZ256rri", - "VPCMPUDZrri", - "VPCMPUQZ128rri", - "VPCMPUQZ256rri", - "VPCMPUQZrri", - "VPCMPUWZ128rri", - "VPCMPUWZ256rri", - "VPCMPUWZrri", - "VPCMPWZ128rri", - "VPCMPWZ256rri", - "VPCMPWZrri", - "VPMAXSQZ128rr", - "VPMAXSQZ256rr", - "VPMAXSQZrr", - "VPMAXUQZ128rr", - "VPMAXUQZ256rr", - "VPMAXUQZrr", - "VPMINSQZ128rr", - "VPMINSQZ256rr", - "VPMINSQZrr", - "VPMINUQZ128rr", - "VPMINUQZ256rr", - "VPMINUQZrr", + "VPCMPB(Z|Z128|Z256)rri", + "VPCMPD(Z|Z128|Z256)rri", + "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", + "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", + "(V?)PCMPGTQ(Y?)rr", + "VPCMPQ(Z|Z128|Z256)rri", + "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", + "VPCMPW(Z|Z128|Z256)rri", + "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr", "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined. - "VPTESTMBZ128rr", - "VPTESTMBZ256rr", - "VPTESTMBZrr", - "VPTESTMDZ128rr", - "VPTESTMDZ256rr", - "VPTESTMDZrr", - "VPTESTMQZ128rr", - "VPTESTMQZ256rr", - "VPTESTMQZrr", - "VPTESTMWZ128rr", - "VPTESTMWZ256rr", - "VPTESTMWZrr", - "VPTESTNMBZ128rr", - "VPTESTNMBZ256rr", - "VPTESTNMBZrr", - "VPTESTNMDZ128rr", - "VPTESTNMDZ256rr", - "VPTESTNMDZrr", - "VPTESTNMQZ128rr", - "VPTESTNMQZ256rr", - "VPTESTNMQZrr", - "VPTESTNMWZ128rr", - "VPTESTNMWZ256rr", - "VPTESTNMWZrr")>; + "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { let Latency = 3; @@ -1152,117 +929,47 @@ def SKXWriteResGroup50 : SchedWriteRes<[SKXPort015]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PSYrr", - "VCVTDQ2PSZ128rr", - "VCVTDQ2PSZ256rr", - "VCVTDQ2PSZrr", +def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z|Z128|Z256)rr", "(V?)CVTDQ2PSrr", - "VCVTPD2QQZ128rr", - "VCVTPD2QQZ256rr", - "VCVTPD2QQZrr", - "VCVTPD2UQQZ128rr", - "VCVTPD2UQQZ256rr", - "VCVTPD2UQQZrr", - "VCVTPS2DQYrr", - "VCVTPS2DQZ128rr", - "VCVTPS2DQZ256rr", - "VCVTPS2DQZrr", + "VCVTPD2QQ(Z|Z128|Z256)rr", + "VCVTPD2UQQ(Z|Z128|Z256)rr", + "VCVTPS2DQ(Y|Z|Z128|Z256)rr", "(V?)CVTPS2DQrr", - "VCVTPS2UDQZ128rr", - "VCVTPS2UDQZ256rr", - "VCVTPS2UDQZrr", - "VCVTQQ2PDZ128rr", - "VCVTQQ2PDZ256rr", - "VCVTQQ2PDZrr", - "VCVTTPD2QQZ128rr", - "VCVTTPD2QQZ256rr", - "VCVTTPD2QQZrr", - "VCVTTPD2UQQZ128rr", - "VCVTTPD2UQQZ256rr", - "VCVTTPD2UQQZrr", - "VCVTTPS2DQYrr", - "VCVTTPS2DQZ128rr", - "VCVTTPS2DQZ256rr", - "VCVTTPS2DQZrr", + "VCVTPS2UDQ(Z|Z128|Z256)rr", + "VCVTQQ2PD(Z|Z128|Z256)rr", + "VCVTTPD2QQ(Z|Z128|Z256)rr", + "VCVTTPD2UQQ(Z|Z128|Z256)rr", + "VCVTTPS2DQ(Y|Z|Z128|Z256)rr", "(V?)CVTTPS2DQrr", - "VCVTTPS2UDQZ128rr", - "VCVTTPS2UDQZ256rr", - "VCVTTPS2UDQZrr", - "VCVTUDQ2PSZ128rr", - "VCVTUDQ2PSZ256rr", - "VCVTUDQ2PSZrr", - "VCVTUQQ2PDZ128rr", - "VCVTUQQ2PDZ256rr", - "VCVTUQQ2PDZrr")>; + "VCVTTPS2UDQ(Z|Z128|Z256)rr", + "VCVTUDQ2PS(Z|Z128|Z256)rr", + "VCVTUQQ2PD(Z|Z128|Z256)rr")>; def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { let Latency = 4; let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPDZ128rr", - "VEXPANDPDZ256rr", - "VEXPANDPDZrr", - "VEXPANDPSZ128rr", - "VEXPANDPSZ256rr", - "VEXPANDPSZrr", - "VPEXPANDDZ128rr", - "VPEXPANDDZ256rr", - "VPEXPANDDZrr", - "VPEXPANDQZ128rr", - "VPEXPANDQZ256rr", - "VPEXPANDQZrr", - "VPMOVDBZ128rr", - "VPMOVDBZ256rr", - "VPMOVDBZrr", - "VPMOVDWZ128rr", - "VPMOVDWZ256rr", - "VPMOVDWZrr", - "VPMOVQBZ128rr", - "VPMOVQBZ256rr", - "VPMOVQBZrr", - "VPMOVQWZ128rr", - "VPMOVQWZ256rr", - "VPMOVQWZrr", - "VPMOVSDBZ128rr", - "VPMOVSDBZ256rr", - "VPMOVSDBZrr", - "VPMOVSDWZ128rr", - "VPMOVSDWZ256rr", - "VPMOVSDWZrr", - "VPMOVSQBZ128rr", - "VPMOVSQBZ256rr", - "VPMOVSQBZrr", - "VPMOVSQDZ128rr", - "VPMOVSQDZ256rr", - "VPMOVSQDZrr", - "VPMOVSQWZ128rr", - "VPMOVSQWZ256rr", - "VPMOVSQWZrr", - "VPMOVSWBZ128rr", - "VPMOVSWBZ256rr", - "VPMOVSWBZrr", - "VPMOVUSDBZ128rr", - "VPMOVUSDBZ256rr", - "VPMOVUSDBZrr", - "VPMOVUSDWZ128rr", - "VPMOVUSDWZ256rr", - "VPMOVUSDWZrr", - "VPMOVUSQBZ128rr", - "VPMOVUSQBZ256rr", - "VPMOVUSQBZrr", - "VPMOVUSQDZ128rr", - "VPMOVUSQDZ256rr", - "VPMOVUSQDZrr", - "VPMOVUSQWZ128rr", - "VPMOVUSQWZ256rr", - "VPMOVUSQWZrr", - "VPMOVUSWBZ128rr", - "VPMOVUSWBZ256rr", - "VPMOVUSWBZrr", - "VPMOVWBZ128rr", - "VPMOVWBZ256rr", - "VPMOVWBZrr")>; +def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", + "VEXPANDPS(Z|Z128|Z256)rr", + "VPEXPANDD(Z|Z128|Z256)rr", + "VPEXPANDQ(Z|Z128|Z256)rr", + "VPMOVDB(Z|Z128|Z256)rr", + "VPMOVDW(Z|Z128|Z256)rr", + "VPMOVQB(Z|Z128|Z256)rr", + "VPMOVQW(Z|Z128|Z256)rr", + "VPMOVSDB(Z|Z128|Z256)rr", + "VPMOVSDW(Z|Z128|Z256)rr", + "VPMOVSQB(Z|Z128|Z256)rr", + "VPMOVSQD(Z|Z128|Z256)rr", + "VPMOVSQW(Z|Z128|Z256)rr", + "VPMOVSWB(Z|Z128|Z256)rr", + "VPMOVUSDB(Z|Z128|Z256)rr", + "VPMOVUSDW(Z|Z128|Z256)rr", + "VPMOVUSQB(Z|Z128|Z256)rr", + "VPMOVUSQD(Z|Z128|Z256)rr", + "VPMOVUSWB(Z|Z128|Z256)rr", + "VPMOVWB(Z|Z128|Z256)rr")>; def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> { let Latency = 4; @@ -1285,9 +992,7 @@ def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { } def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", "IST_F(16|32)m", - "VPMOVQDZ128mr(b?)", - "VPMOVQDZ256mr(b?)", - "VPMOVQDZmr(b?)")>; + "VPMOVQD(Z|Z128|Z256)mr(b?)")>; def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { let Latency = 4; @@ -1342,53 +1047,38 @@ def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup61], (instregex "CVTPD2DQrr", - "CVTPD2PSrr", - "CVTPS2PDrr", - "CVTSD2SSrr", - "CVTSI642SDrr", - "CVTSI2SDrr", - "CVTSI2SSrr", - "CVTSS2SDrr", - "CVTTPD2DQrr", - "MMX_CVTPD2PIirr", - "MMX_CVTPS2PIirr", - "MMX_CVTTPD2PIirr", - "MMX_CVTTPS2PIirr", +def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", + "MMX_CVT(T?)PS2PIirr", "VCVTDQ2PDZ128rr", "VCVTPD2DQZ128rr", - "VCVTPD2DQrr", + "(V?)CVT(T?)PD2DQrr", "VCVTPD2PSZ128rr", - "VCVTPD2PSrr", + "(V?)CVTPD2PSrr", "VCVTPD2UDQZ128rr", "VCVTPH2PSZ128rr", "VCVTPH2PSrr", "VCVTPS2PDZ128rr", - "VCVTPS2PDrr", + "(V?)CVTPS2PDrr", "VCVTPS2PHZ128rr", "VCVTPS2PHrr", "VCVTPS2QQZ128rr", "VCVTPS2UQQZ128rr", "VCVTQQ2PSZ128rr", - "VCVTSD2SSrr", - "VCVTSI642SDrr", - "VCVTSI2SDZrr", - "VCVTSI2SDrr", + "(V?)CVTSD2SSrr", + "(V?)CVTSI(64)?2SDrr", "VCVTSI2SSZrr", - "VCVTSI2SSrr", - "VCVTSI642SDZrr", + "(V?)CVTSI2SSrr", + "VCVTSI(64)?2SDZrr", "VCVTSS2SDZrr", - "VCVTSS2SDrr", + "(V?)CVTSS2SDrr", "VCVTTPD2DQZ128rr", - "VCVTTPD2DQrr", "VCVTTPD2UDQZ128rr", "VCVTTPS2QQZ128rr", "VCVTTPS2UQQZ128rr", "VCVTUDQ2PDZ128rr", "VCVTUQQ2PSZ128rr", - "VCVTUSI2SDZrr", "VCVTUSI2SSZrr", - "VCVTUSI642SDZrr")>; + "VCVTUSI(64)?2SDZrr")>; def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { let Latency = 5; @@ -1425,57 +1115,23 @@ def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { let NumMicroOps = 4; let ResourceCycles = [1,2,1]; } -def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDBZ128mr(b?)", - "VPMOVDBZ256mr(b?)", - "VPMOVDBZmr(b?)", - "VPMOVDWZ128mr(b?)", - "VPMOVDWZ256mr(b?)", - "VPMOVDWZmr(b?)", - "VPMOVQBZ128mr(b?)", - "VPMOVQBZ256mr(b?)", - "VPMOVQBZmr(b?)", - "VPMOVQWZ128mr(b?)", - "VPMOVQWZ256mr(b?)", - "VPMOVQWZmr(b?)", - "VPMOVSDBZ128mr(b?)", - "VPMOVSDBZ256mr(b?)", - "VPMOVSDBZmr(b?)", - "VPMOVSDWZ128mr(b?)", - "VPMOVSDWZ256mr(b?)", - "VPMOVSDWZmr(b?)", - "VPMOVSQBZ128mr(b?)", - "VPMOVSQBZ256mr(b?)", - "VPMOVSQBZmr(b?)", - "VPMOVSQDZ128mr(b?)", - "VPMOVSQDZ256mr(b?)", - "VPMOVSQDZmr(b?)", - "VPMOVSQWZ128mr(b?)", - "VPMOVSQWZ256mr(b?)", - "VPMOVSQWZmr(b?)", - "VPMOVSWBZ128mr(b?)", - "VPMOVSWBZ256mr(b?)", - "VPMOVSWBZmr(b?)", - "VPMOVUSDBZ128mr(b?)", - "VPMOVUSDBZ256mr(b?)", - "VPMOVUSDBZmr(b?)", - "VPMOVUSDWZ128mr(b?)", - "VPMOVUSDWZ256mr(b?)", - "VPMOVUSDWZmr(b?)", - "VPMOVUSQBZ128mr(b?)", - "VPMOVUSQBZ256mr(b?)", - "VPMOVUSQBZmr(b?)", - "VPMOVUSQDZ128mr(b?)", - "VPMOVUSQDZ256mr(b?)", - "VPMOVUSQDZmr(b?)", - "VPMOVUSQWZ128mr(b?)", - "VPMOVUSQWZ256mr(b?)", - "VPMOVUSQWZmr(b?)", - "VPMOVUSWBZ128mr(b?)", - "VPMOVUSWBZ256mr(b?)", - "VPMOVUSWBZmr(b?)", - "VPMOVWBZ128mr(b?)", - "VPMOVWBZ256mr(b?)", - "VPMOVWBZmr(b?)")>; +def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", + "VPMOVDW(Z|Z128|Z256)mr(b?)", + "VPMOVQB(Z|Z128|Z256)mr(b?)", + "VPMOVQW(Z|Z128|Z256)mr(b?)", + "VPMOVSDB(Z|Z128|Z256)mr(b?)", + "VPMOVSDW(Z|Z128|Z256)mr(b?)", + "VPMOVSQB(Z|Z128|Z256)mr(b?)", + "VPMOVSQD(Z|Z128|Z256)mr(b?)", + "VPMOVSQW(Z|Z128|Z256)mr(b?)", + "VPMOVSWB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDB(Z|Z128|Z256)mr(b?)", + "VPMOVUSDW(Z|Z128|Z256)mr(b?)", + "VPMOVUSQB(Z|Z128|Z256)mr(b?)", + "VPMOVUSQD(Z|Z128|Z256)mr(b?)", + "VPMOVUSQW(Z|Z128|Z256)mr(b?)", + "VPMOVUSWB(Z|Z128|Z256)mr(b?)", + "VPMOVWB(Z|Z128|Z256)mr(b?)")>; def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { let Latency = 5; @@ -1534,21 +1190,11 @@ def SKXWriteResGroup72 : SchedWriteRes<[SKXPort0]> { let ResourceCycles = [2]; } def: InstRW<[SKXWriteResGroup72], (instregex "MMX_CVTPI2PSirr", - "VCOMPRESSPDZ128rr", - "VCOMPRESSPDZ256rr", - "VCOMPRESSPDZrr", - "VCOMPRESSPSZ128rr", - "VCOMPRESSPSZ256rr", - "VCOMPRESSPSZrr", - "VPCOMPRESSDZ128rr", - "VPCOMPRESSDZ256rr", - "VPCOMPRESSDZrr", - "VPCOMPRESSQZ128rr", - "VPCOMPRESSQZ256rr", - "VPCOMPRESSQZrr", - "VPERMWZ128rr", - "VPERMWZ256rr", - "VPERMWZrr")>; + "VCOMPRESSPD(Z|Z128|Z256)rr", + "VCOMPRESSPS(Z|Z128|Z256)rr", + "VPCOMPRESSD(Z|Z128|Z256)rr", + "VPCOMPRESSQ(Z|Z128|Z256)rr", + "VPERMW(Z|Z128|Z256)rr")>; def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { let Latency = 6; @@ -1581,27 +1227,17 @@ def SKXWriteResGroup74 : SchedWriteRes<[SKXPort0,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup74], (instregex "CVTSD2SI64rr", - "CVTSD2SIrr", - "CVTSS2SI64rr", - "CVTSS2SIrr", - "CVTTSD2SI64rr", - "CVTTSD2SIrr", - "VCVTSD2SI64Zrr", - "VCVTSD2SI64rr", - "VCVTSD2SIZrr", - "VCVTSD2SIrr", - "VCVTSD2USI64Zrr", - "VCVTSD2USIZrr", - "VCVTSS2SI64Zrr", - "VCVTSS2SI64rr", - "VCVTSS2SIZrr", - "VCVTSS2SIrr", +def: InstRW<[SKXWriteResGroup74], (instregex "CVTSD2SI(64)?rr", + "CVTSS2SI(64)?rr", + "CVTTSD2SI(64)?rr", + "VCVTSD2SI(64)?Zrr", + "VCVTSD2SI(64)?rr", + "VCVTSD2USI(64)?Zrr", + "VCVTSS2SI(64)?Zrr", + "VCVTSS2SI(64)?rr", "VCVTSS2USIZrr", - "VCVTTSD2SI64Zrr(b?)", - "VCVTTSD2SI64rr", - "VCVTTSD2SIZrr(b?)", - "VCVTTSD2SIrr", + "VCVTTSD2SI(64)?Zrr(b?)", + "VCVTTSD2SI(64)?rr", "VCVTTSD2USI64Zrr(b?)", "VCVTTSD2USIZrr(b?)", "VCVTTSS2USIZrr(b?)")>; @@ -1671,8 +1307,7 @@ def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[SKXWriteResGroup82], (instregex "CVTSI642SSrr", - "VCVTSI642SSrr", +def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", "VCVTSI642SSZrr", "VCVTUSI642SSZrr")>; @@ -1811,44 +1446,22 @@ def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", - "VCVTDQ2PDZrr", - "VCVTPD2DQYrr", - "VCVTPD2DQZ256rr", - "VCVTPD2DQZrr", - "VCVTPD2PSYrr", - "VCVTPD2PSZ256rr", - "VCVTPD2PSZrr", - "VCVTPD2UDQZ256rr", - "VCVTPD2UDQZrr", - "VCVTPH2PSYrr", - "VCVTPH2PSZ256rr", - "VCVTPH2PSZrr", - "VCVTPS2PDYrr", - "VCVTPS2PDZ256rr", - "VCVTPS2PDZrr", - "VCVTPS2PHYrr", - "VCVTPS2PHZ256rr", - "VCVTPS2PHZrr", - "VCVTPS2QQZ256rr", - "VCVTPS2QQZrr", - "VCVTPS2UQQZ256rr", - "VCVTPS2UQQZrr", - "VCVTQQ2PSZ256rr", - "VCVTQQ2PSZrr", - "VCVTTPD2DQYrr", - "VCVTTPD2DQZ256rr", - "VCVTTPD2DQZrr", - "VCVTTPD2UDQZ256rr", - "VCVTTPD2UDQZrr", - "VCVTTPS2QQZ256rr", - "VCVTTPS2QQZrr", - "VCVTTPS2UQQZ256rr", - "VCVTTPS2UQQZrr", - "VCVTUDQ2PDZ256rr", - "VCVTUDQ2PDZrr", - "VCVTUQQ2PSZ256rr", - "VCVTUQQ2PSZrr")>; +def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PD(Z|Z256)rr", + "VCVTPD2DQ(Y|Z|Z256)rr", + "VCVTPD2PS(Y|Z|Z256)rr", + "VCVTPD2UDQ(Z|Z256)rr", + "VCVTPH2PS(Y|Z|Z256)rr", + "VCVTPS2PD(Y|Z|Z256)rr", + "VCVTPS2PH(Y|Z|Z256)rr", + "VCVTPS2QQ(Z|Z256)rr", + "VCVTPS2UQQ(Z|Z256)rr", + "VCVTQQ2PS(Z|Z256)rr", + "VCVTTPD2DQ(Y|Z|Z256)rr", + "VCVTTPD2UDQ(Z|Z256)rr", + "VCVTTPS2QQ(Z|Z256)rr", + "VCVTTPS2UQQ(Z|Z256)rr", + "VCVTUDQ2PD(Z|Z256)rr", + "VCVTUQQ2PS(Z|Z256)rr")>; def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { @@ -1876,29 +1489,14 @@ def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)", "VMOVSLDUPZ128rm(b?)", "VMOVUPDZ128rm(b?)", "VMOVUPSZ128rm(b?)", - "VPADDBZ128rm(b?)", - "(V?)PADDBrm", - "VPADDDZ128rm(b?)", - "(V?)PADDDrm", - "VPADDQZ128rm(b?)", - "(V?)PADDQrm", - "VPADDWZ128rm(b?)", - "(V?)PADDWrm", + "VPADD(B|D|Q|W)Z128rm(b?)", + "(V?)PADD(B|D|Q|W)rm", "VPBLENDDrmi", - "VPBLENDMBZ128rm(b?)", - "VPBLENDMDZ128rm(b?)", - "VPBLENDMQZ128rm(b?)", - "VPBLENDMWZ128rm(b?)", + "VPBLENDM(B|D|Q|W)Z128rm(b?)", "VPBROADCASTDZ128m(b?)", "VPBROADCASTQZ128m(b?)", - "VPSUBBZ128rm(b?)", - "(V?)PSUBBrm", - "VPSUBDZ128rm(b?)", - "(V?)PSUBDrm", - "VPSUBQZ128rm(b?)", - "(V?)PSUBQrm", - "VPSUBWZ128rm(b?)", - "(V?)PSUBWrm", + "VPSUB(B|D|Q|W)Z128rm(b?)", + "(V?)PSUB(B|D|Q|W)rm", "VPTERNLOGDZ128rm(b?)i", "VPTERNLOGQZ128rm(b?)i")>; @@ -1943,13 +1541,9 @@ def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup100], (instregex "CVTTSS2SI64rr", - "CVTTSS2SIrr", - "VCVTSS2USI64Zrr", - "VCVTTSS2SI64Zrr", - "VCVTTSS2SI64rr", - "VCVTTSS2SIZrr", - "VCVTTSS2SIrr", +def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", + "VCVTTSS2SI(64)?Zrr", + "(V?)CVTTSS2SI(64)?rr", "VCVTTSS2USI64Zrr")>; def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { @@ -1964,10 +1558,7 @@ def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup103], (instregex "KMOVBkm", - "KMOVDkm", - "KMOVQkm", - "KMOVWkm")>; +def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { let Latency = 7; @@ -1982,18 +1573,10 @@ def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { let NumMicroOps = 4; let ResourceCycles = [1,2,1]; } -def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPDZ128mr(b?)", - "VCOMPRESSPDZ256mr(b?)", - "VCOMPRESSPDZmr(b?)", - "VCOMPRESSPSZ128mr(b?)", - "VCOMPRESSPSZ256mr(b?)", - "VCOMPRESSPSZmr(b?)", - "VPCOMPRESSDZ128mr(b?)", - "VPCOMPRESSDZ256mr(b?)", - "VPCOMPRESSDZmr(b?)", - "VPCOMPRESSQZ128mr(b?)", - "VPCOMPRESSQZ256mr(b?)", - "VPCOMPRESSQZmr(b?)")>; +def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", + "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", + "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { let Latency = 7; @@ -2091,18 +1674,14 @@ def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup119], (instregex "FCOM32m", - "FCOM64m", - "FCOMP32m", - "FCOMP64m", +def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)32m", + "FCOM(P?)64m", "MMX_PSADBWirm", "VFPCLASSSDrm(b?)", "VPBROADCASTBYrm", - "VPBROADCASTBZ256m(b?)", - "VPBROADCASTBZm(b?)", + "VPBROADCASTB(Z|Z256)m(b?)", "VPBROADCASTWYrm", - "VPBROADCASTWZ256m(b?)", - "VPBROADCASTWZm(b?)", + "VPBROADCASTW(Z|Z256)m(b?)", "VPMOVSXBDYrm", "VPMOVSXBQYrm", "VPMOVSXWQYrm")>; @@ -2112,10 +1691,8 @@ def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPDZ256rm(b?)", - "VBLENDMPDZrm(b?)", - "VBLENDMPSZ256rm(b?)", - "VBLENDMPSZrm(b?)", +def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)", + "VBLENDMPS(Z|Z256)rm(b?)", "VBROADCASTF32X2Z256m(b?)", "VBROADCASTF32X2Zm(b?)", "VBROADCASTF32X4Z256rm(b?)", @@ -2132,89 +1709,40 @@ def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPDZ256rm(b?)", "VBROADCASTI64X2Z128rm(b?)", "VBROADCASTI64X2rm(b?)", "VBROADCASTI64X4rm(b?)", - "VBROADCASTSDZ256m(b?)", - "VBROADCASTSDZm(b?)", - "VBROADCASTSSZ256m(b?)", - "VBROADCASTSSZm(b?)", - "VINSERTF32x4Z256rm(b?)", - "VINSERTF32x4Zrm(b?)", + "VBROADCASTSD(Z|Z256)m(b?)", + "VBROADCASTSS(Z|Z256)m(b?)", + "VINSERTF32x4(Z|Z256)rm(b?)", "VINSERTF32x8Zrm(b?)", - "VINSERTF64x2Z256rm(b?)", - "VINSERTF64x2Zrm(b?)", + "VINSERTF64x2(Z|Z256)rm(b?)", "VINSERTF64x4Zrm(b?)", - "VINSERTI32x4Z256rm(b?)", - "VINSERTI32x4Zrm(b?)", + "VINSERTI32x4(Z|Z256)rm(b?)", "VINSERTI32x8Zrm(b?)", - "VINSERTI64x2Z256rm(b?)", - "VINSERTI64x2Zrm(b?)", + "VINSERTI64x2(Z|Z256)rm(b?)", "VINSERTI64x4Zrm(b?)", - "VMOVAPDZ256rm(b?)", - "VMOVAPDZrm(b?)", - "VMOVAPSZ256rm(b?)", - "VMOVAPSZrm(b?)", - "VMOVDDUPZ256rm(b?)", - "VMOVDDUPZrm(b?)", - "VMOVDQA32Z256rm(b?)", - "VMOVDQA32Zrm(b?)", - "VMOVDQA64Z256rm(b?)", - "VMOVDQA64Zrm(b?)", - "VMOVDQU16Z256rm(b?)", - "VMOVDQU16Zrm(b?)", - "VMOVDQU32Z256rm(b?)", - "VMOVDQU32Zrm(b?)", - "VMOVDQU64Z256rm(b?)", - "VMOVDQU64Zrm(b?)", - "VMOVDQU8Z256rm(b?)", - "VMOVDQU8Zrm(b?)", + "VMOVAPD(Z|Z256)rm(b?)", + "VMOVAPS(Z|Z256)rm(b?)", + "VMOVDDUP(Z|Z256)rm(b?)", + "VMOVDQA32(Z|Z256)rm(b?)", + "VMOVDQA64(Z|Z256)rm(b?)", + "VMOVDQU16(Z|Z256)rm(b?)", + "VMOVDQU32(Z|Z256)rm(b?)", + "VMOVDQU64(Z|Z256)rm(b?)", + "VMOVDQU8(Z|Z256)rm(b?)", "VMOVNTDQAZ256rm(b?)", - "VMOVSHDUPZ256rm(b?)", - "VMOVSHDUPZrm(b?)", - "VMOVSLDUPZ256rm(b?)", - "VMOVSLDUPZrm(b?)", - "VMOVUPDZ256rm(b?)", - "VMOVUPDZrm(b?)", - "VMOVUPSZ256rm(b?)", - "VMOVUPSZrm(b?)", - "VPADDBYrm", - "VPADDBZ256rm(b?)", - "VPADDBZrm(b?)", - "VPADDDYrm", - "VPADDDZ256rm(b?)", - "VPADDDZrm(b?)", - "VPADDQYrm", - "VPADDQZ256rm(b?)", - "VPADDQZrm(b?)", - "VPADDWYrm", - "VPADDWZ256rm(b?)", - "VPADDWZrm(b?)", + "VMOVSHDUP(Z|Z256)rm(b?)", + "VMOVSLDUP(Z|Z256)rm(b?)", + "VMOVUPD(Z|Z256)rm(b?)", + "VMOVUPS(Z|Z256)rm(b?)", + "VPADD(B|D|Q|W)Yrm", + "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", "VPBLENDDYrmi", - "VPBLENDMBZ256rm(b?)", - "VPBLENDMBZrm(b?)", - "VPBLENDMDZ256rm(b?)", - "VPBLENDMDZrm(b?)", - "VPBLENDMQZ256rm(b?)", - "VPBLENDMQZrm(b?)", - "VPBLENDMWZ256rm(b?)", - "VPBLENDMWZrm(b?)", - "VPBROADCASTDZ256m(b?)", - "VPBROADCASTDZm(b?)", - "VPBROADCASTQZ256m(b?)", - "VPBROADCASTQZm(b?)", - "VPSUBBYrm", - "VPSUBBZ256rm(b?)", - "VPSUBBZrm(b?)", - "VPSUBDYrm", - "VPSUBDZ256rm(b?)", - "VPSUBDZrm(b?)", - "VPSUBQYrm", - "VPSUBQZ256rm(b?)", - "VPSUBQZrm(b?)", - "VPSUBWYrm", - "VPSUBWZrm(b?)", - "VPTERNLOGDZ256rm(b?)i", - "VPTERNLOGDZrm(b?)i", - "VPTERNLOGQZ256rm(b?)i", - "VPTERNLOGQZrm(b?)i")>; + "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", + "VPBROADCASTD(Z|Z256)m(b?)", + "VPBROADCASTQ(Z|Z256)m(b?)", + "VPSUB(B|D|Q|W)Yrm", + "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", + "VPTERNLOGD(Z|Z256)rm(b?)i", + "VPTERNLOGQ(Z|Z256)rm(b?)i")>; def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { let Latency = 8; @@ -2329,20 +1857,11 @@ def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i", "VFPCLASSSSrm(b?)", "VPCMPBZ128rmi(b?)", "VPCMPDZ128rmi(b?)", - "VPCMPEQBZ128rm(b?)", - "VPCMPEQDZ128rm(b?)", - "VPCMPEQQZ128rm(b?)", - "VPCMPEQWZ128rm(b?)", - "VPCMPGTBZ128rm(b?)", - "VPCMPGTDZ128rm(b?)", - "VPCMPGTQZ128rm(b?)", + "VPCMPEQ(B|D|Q|W)Z128rm(b?)", + "VPCMPGT(B|D|Q|W)Z128rm(b?)", "(V?)PCMPGTQrm", - "VPCMPGTWZ128rm(b?)", "VPCMPQZ128rmi(b?)", - "VPCMPUBZ128rmi(b?)", - "VPCMPUDZ128rmi(b?)", - "VPCMPUQZ128rmi(b?)", - "VPCMPUWZ128rmi(b?)", + "VPCMPU(B|D|Q|W)Z128rmi(b?)", "VPCMPWZ128rmi(b?)", "VPERMI2D128rm(b?)", "VPERMI2PD128rm(b?)", @@ -2386,8 +1905,7 @@ def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVTPS2PIirm", - "MMX_CVTTPS2PIirm", +def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", "VCVTPH2PSrm", "(V?)CVTPS2PDrm")>; @@ -2439,90 +1957,48 @@ def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { } def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", "ILD_F(16|32|64)m", - "VALIGNDZ256rm(b?)i", - "VALIGNDZrm(b?)i", - "VALIGNQZ256rm(b?)i", - "VALIGNQZrm(b?)i", - "VCMPPDZ256rm(b?)i", - "VCMPPDZrm(b?)i", - "VCMPPSZ256rm(b?)i", - "VCMPPSZrm(b?)i", - "VPCMPBZ256rmi(b?)", - "VPCMPBZrmi(b?)", - "VPCMPDZ256rmi(b?)", - "VPCMPDZrmi(b?)", - "VPCMPEQBZ256rm(b?)", - "VPCMPEQBZrm(b?)", - "VPCMPEQDZ256rm(b?)", - "VPCMPEQDZrm(b?)", - "VPCMPEQQZ256rm(b?)", - "VPCMPEQQZrm(b?)", - "VPCMPEQWZ256rm(b?)", - "VPCMPEQWZrm(b?)", - "VPCMPGTBZ256rm(b?)", - "VPCMPGTBZrm(b?)", - "VPCMPGTDZ256rm(b?)", - "VPCMPGTDZrm(b?)", + "VALIGND(Z|Z256)rm(b?)i", + "VALIGNQ(Z|Z256)rm(b?)i", + "VCMPPD(Z|Z256)rm(b?)i", + "VCMPPS(Z|Z256)rm(b?)i", + "VPCMPB(Z|Z256)rmi(b?)", + "VPCMPD(Z|Z256)rmi(b?)", + "VPCMPEQB(Z|Z256)rm(b?)", + "VPCMPEQD(Z|Z256)rm(b?)", + "VPCMPEQQ(Z|Z256)rm(b?)", + "VPCMPEQW(Z|Z256)rm(b?)", + "VPCMPGTB(Z|Z256)rm(b?)", + "VPCMPGTD(Z|Z256)rm(b?)", "VPCMPGTQYrm", - "VPCMPGTQZ256rm(b?)", - "VPCMPGTQZrm(b?)", - "VPCMPGTWZ256rm(b?)", - "VPCMPGTWZrm(b?)", - "VPCMPQZ256rmi(b?)", - "VPCMPQZrmi(b?)", - "VPCMPUBZ256rmi(b?)", - "VPCMPUBZrmi(b?)", - "VPCMPUDZ256rmi(b?)", - "VPCMPUDZrmi(b?)", - "VPCMPUQZ256rmi(b?)", - "VPCMPUQZrmi(b?)", - "VPCMPUWZ256rmi(b?)", - "VPCMPUWZrmi(b?)", - "VPCMPWZ256rmi(b?)", - "VPCMPWZrmi(b?)", - "VPMAXSQZ256rm(b?)", - "VPMAXSQZrm(b?)", - "VPMAXUQZ256rm(b?)", - "VPMAXUQZrm(b?)", - "VPMINSQZ256rm(b?)", - "VPMINSQZrm(b?)", - "VPMINUQZ256rm(b?)", - "VPMINUQZrm(b?)", - "VPTESTMBZ256rm(b?)", - "VPTESTMBZrm(b?)", - "VPTESTMDZ256rm(b?)", - "VPTESTMDZrm(b?)", - "VPTESTMQZ256rm(b?)", - "VPTESTMQZrm(b?)", - "VPTESTMWZ256rm(b?)", - "VPTESTMWZrm(b?)", - "VPTESTNMBZ256rm(b?)", - "VPTESTNMBZrm(b?)", - "VPTESTNMDZ256rm(b?)", - "VPTESTNMDZrm(b?)", - "VPTESTNMQZ256rm(b?)", - "VPTESTNMQZrm(b?)", - "VPTESTNMWZ256rm(b?)", - "VPTESTNMWZrm(b?)")>; + "VPCMPGTQ(Z|Z256)rm(b?)", + "VPCMPGTW(Z|Z256)rm(b?)", + "VPCMPQ(Z|Z256)rmi(b?)", + "VPCMPU(B|D|Q|W)Z256rmi(b?)", + "VPCMPU(B|D|Q|W)Zrmi(b?)", + "VPCMPW(Z|Z256)rmi(b?)", + "VPMAXSQ(Z|Z256)rm(b?)", + "VPMAXUQ(Z|Z256)rm(b?)", + "VPMINSQ(Z|Z256)rm(b?)", + "VPMINUQ(Z|Z256)rm(b?)", + "VPTESTM(B|D|Q|W)Z256rm(b?)", + "VPTESTM(B|D|Q|W)Zrm(b?)", + "VPTESTNM(B|D|Q|W)Z256rm(b?)", + "VPTESTNM(B|D|Q|W)Zrm(b?)")>; def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { let Latency = 10; let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup149], (instregex "CVTDQ2PSrm", - "CVTPS2DQrm", - "CVTSS2SDrm", - "CVTTPS2DQrm", - "VCVTDQ2PDZ128rm(b?)", +def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", "VCVTDQ2PSZ128rm(b?)", - "VCVTDQ2PSrm", + "(V?)CVTDQ2PSrm", "VCVTPD2QQZ128rm(b?)", "VCVTPD2UQQZ128rm(b?)", "VCVTPH2PSYrm", "VCVTPH2PSZ128rm(b?)", "VCVTPS2DQZ128rm(b?)", - "VCVTPS2DQrm", + "(V?)CVTPS2DQrm", "VCVTPS2PDZ128rm(b?)", "VCVTPS2QQZ128rm(b?)", "VCVTPS2UDQZ128rm(b?)", @@ -2530,11 +2006,11 @@ def: InstRW<[SKXWriteResGroup149], (instregex "CVTDQ2PSrm", "VCVTQQ2PDZ128rm(b?)", "VCVTQQ2PSZ128rm(b?)", "VCVTSS2SDZrm", - "VCVTSS2SDrm", + "(V?)CVTSS2SDrm", "VCVTTPD2QQZ128rm(b?)", "VCVTTPD2UQQZ128rm(b?)", "VCVTTPS2DQZ128rm(b?)", - "VCVTTPS2DQrm", + "(V?)CVTTPS2DQrm", "VCVTTPS2QQZ128rm(b?)", "VCVTTPS2UDQZ128rm(b?)", "VCVTTPS2UQQZ128rm(b?)", @@ -2608,47 +2084,24 @@ def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PDZ256rm(b?)", - "VCVTDQ2PDZrm(b?)", +def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PD(Z|Z256)rm(b?)", "VCVTDQ2PSYrm", - "VCVTDQ2PSZ256rm(b?)", - "VCVTDQ2PSZrm(b?)", - "VCVTPD2QQZ256rm(b?)", - "VCVTPD2QQZrm(b?)", - "VCVTPD2UQQZ256rm(b?)", - "VCVTPD2UQQZrm(b?)", - "VCVTPH2PSZ256rm(b?)", - "VCVTPH2PSZrm(b?)", - "VCVTPS2DQYrm", - "VCVTPS2DQZ256rm(b?)", - "VCVTPS2DQZrm(b?)", + "VCVTDQ2PS(Z|Z256)rm(b?)", + "VCVTPH2PS(Z|Z256)rm(b?)", "VCVTPS2PDYrm", - "VCVTPS2PDZ256rm(b?)", - "VCVTPS2PDZrm(b?)", - "VCVTPS2QQZ256rm(b?)", - "VCVTPS2UDQZ256rm(b?)", - "VCVTPS2UDQZrm(b?)", - "VCVTPS2UQQZ256rm(b?)", - "VCVTQQ2PDZ256rm(b?)", - "VCVTQQ2PDZrm(b?)", + "VCVTPS2PD(Z|Z256)rm(b?)", + "VCVTQQ2PD(Z|Z256)rm(b?)", "VCVTQQ2PSZ256rm(b?)", - "VCVTTPD2QQZ256rm(b?)", - "VCVTTPD2QQZrm(b?)", - "VCVTTPD2UQQZ256rm(b?)", - "VCVTTPD2UQQZrm(b?)", - "VCVTTPS2DQYrm", - "VCVTTPS2DQZ256rm(b?)", - "VCVTTPS2DQZrm(b?)", - "VCVTTPS2QQZ256rm(b?)", - "VCVTTPS2UDQZ256rm(b?)", - "VCVTTPS2UDQZrm(b?)", - "VCVTTPS2UQQZ256rm(b?)", - "VCVTUDQ2PDZ256rm(b?)", - "VCVTUDQ2PDZrm(b?)", - "VCVTUDQ2PSZ256rm(b?)", - "VCVTUDQ2PSZrm(b?)", - "VCVTUQQ2PDZ256rm(b?)", - "VCVTUQQ2PDZrm(b?)", + "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", + "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2DQYrm", + "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2QQZ256rm(b?)", + "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", + "VCVT(T?)PS2UQQZ256rm(b?)", + "VCVTUDQ2PD(Z|Z256)rm(b?)", + "VCVTUDQ2PS(Z|Z256)rm(b?)", + "VCVTUQQ2PD(Z|Z256)rm(b?)", "VCVTUQQ2PSZ256rm(b?)")>; def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { @@ -2656,18 +2109,12 @@ def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[SKXWriteResGroup162], (instregex "FICOM16m", - "FICOM32m", - "FICOMP16m", - "FICOMP32m", - "VEXPANDPDZ256rm(b?)", - "VEXPANDPDZrm(b?)", - "VEXPANDPSZ256rm(b?)", - "VEXPANDPSZrm(b?)", - "VPEXPANDDZ256rm(b?)", - "VPEXPANDDZrm(b?)", - "VPEXPANDQZ256rm(b?)", - "VPEXPANDQZrm(b?)")>; +def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)16m", + "FICOM(P?)32m", + "VEXPANDPD(Z|Z256)rm(b?)", + "VEXPANDPS(Z|Z256)rm(b?)", + "VPEXPANDD(Z|Z256)rm(b?)", + "VPEXPANDQ(Z|Z256)rm(b?)")>; def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { let Latency = 11; @@ -2721,11 +2168,9 @@ def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2DQrm", - "CVTPD2PSrm", - "CVTTPD2DQrm", - "MMX_CVTPD2PIirm", - "MMX_CVTTPD2PIirm")>; +def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2PSrm", + "CVT(T?)PD2DQrm", + "MMX_CVT(T?)PD2PIirm")>; def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { let Latency = 11; @@ -2769,9 +2214,7 @@ def SKXWriteResGroup174 : SchedWriteRes<[SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [3]; } -def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQZ128rr", - "VPMULLQZ256rr", - "VPMULLQZrr")>; +def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z|Z128|Z256)rr")>; def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { let Latency = 12; @@ -2785,20 +2228,16 @@ def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup176], (instregex "VCVTSD2USIZrm(b?)", - "VCVTSS2USI64Zrm(b?)", - "VCVTTSD2USIZrm(b?)", - "VCVTTSS2USI64Zrm(b?)")>; +def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", + "VCVT(T?)SS2USI64Zrm(b?)")>; def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { let Latency = 12; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup177], (instregex "VCVTPS2QQZrm(b?)", - "VCVTPS2UQQZrm(b?)", - "VCVTTPS2QQZrm(b?)", - "VCVTTPS2UQQZrm(b?)")>; +def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", + "VCVT(T?)PS2UQQZrm(b?)")>; def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { let Latency = 12;