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Add a couple of missing vsx load and store intrinsics. 

Patch by Jing Yu!

llvm-svn: 266122
This commit is contained in:
Eric Christopher 2016-04-12 21:08:54 +00:00
parent 173ee84530
commit d5c75eed44
2 changed files with 20 additions and 0 deletions
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10
clang/lib/Headers/altivec.h
View File

@ -10283,6 +10283,11 @@ vec_vsx_ld(int __a, const vector float *__b) {
return (vector float)__builtin_vsx_lxvw4x(__a, __b);
}
static __inline__ vector float __ATTRS_o_ai vec_vsx_ld(int __a,
const float *__b) {
return (vector float)__builtin_vsx_lxvw4x(__a, __b);
}
static __inline__ vector signed long long __ATTRS_o_ai
vec_vsx_ld(int __a, const vector signed long long *__b) {
return (vector signed long long)__builtin_vsx_lxvd2x(__a, __b);
@ -10374,6 +10379,11 @@ static __inline__ void __ATTRS_o_ai vec_vsx_st(vector float __a, int __b,
__builtin_vsx_stxvw4x((vector int)__a, __b, __c);
}
static __inline__ void __ATTRS_o_ai vec_vsx_st(vector float __a, int __b,
float *__c) {
__builtin_vsx_stxvw4x((vector int)__a, __b, __c);
}
static __inline__ void __ATTRS_o_ai vec_vsx_st(vector signed long long __a,
int __b,
vector signed long long *__c) {

10
clang/test/CodeGen/builtins-ppc-vsx.c
View File

@ -18,6 +18,7 @@ vector signed long long vsll = { 255LL, -937LL };
vector unsigned long long vull = { 1447LL, 2894LL };
vector signed short vss = { -1, 2, -3, 4, -5, 6, -7, 8 };
vector unsigned short vus = { 0, 1, 2, 3, 4, 5, 6, 7 };
float f = 12.34;
double d = 23.4;
signed char sc = -128;
unsigned char uc = 1;
@ -38,6 +39,7 @@ vector bool char res_vbc;
vector signed char res_vsc;
vector unsigned char res_vuc;
float res_f;
double res_d;
signed int res_si;
unsigned int res_ui;
@ -333,6 +335,10 @@ void test1() {
res_vf = vec_vsx_ld (0, &vf);
// CHECK: @llvm.ppc.vsx.lxvw4x
// CHECK-LE: @llvm.ppc.vsx.lxvw4x
res_vf = vec_vsx_ld (0, &f);
// CHECK: @llvm.ppc.vsx.lxvw4x
// CHECK-LE: @llvm.ppc.vsx.lxvw4x
res_vsll = vec_vsx_ld(0, &vsll);
@ -411,6 +417,10 @@ void test1() {
vec_vsx_st(vf, 0, &res_vf);
// CHECK: @llvm.ppc.vsx.stxvw4x
// CHECK-LE: @llvm.ppc.vsx.stxvw4x
vec_vsx_st(vf, 0, &res_f);
// CHECK: @llvm.ppc.vsx.stxvw4x
// CHECK-LE: @llvm.ppc.vsx.stxvw4x
vec_vsx_st(vsll, 0, &res_vsll);