forked from OSchip/llvm-project
AMDGPU: Fold FP clamp as modifier bit
The manual is unclear on the details of this. It's not clear to me if denormals are not allowed with clamp, or if that is only omod. Not allowing denorms for fp16 or fp64 isn't useful so I also question if that is really a restriction. Same with whether this is valid without IEEE mode enabled. llvm-svn: 295905
This commit is contained in:
Matt Arsenault
parent
f2cce02eb2
commit
d5c6515b68
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@ -65,8 +65,8 @@ enum : uint64_t {
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SOPK_ZEXT = UINT64_C(1) << 38,
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SCALAR_STORE = UINT64_C(1) << 39,
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FIXED_SIZE = UINT64_C(1) << 40,
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VOPAsmPrefer32Bit = UINT64_C(1) << 41
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VOPAsmPrefer32Bit = UINT64_C(1) << 41,
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HasFPClamp = UINT64_C(1) << 42
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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@ -66,6 +66,7 @@ public:
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MachineRegisterInfo *MRI;
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const SIInstrInfo *TII;
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const SIRegisterInfo *TRI;
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const SISubtarget *ST;
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void foldOperand(MachineOperand &OpToFold,
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MachineInstr *UseMI,
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@ -75,6 +76,9 @@ public:
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void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
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const MachineOperand *isClamp(const MachineInstr &MI) const;
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bool tryFoldClamp(MachineInstr &MI);
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public:
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SIFoldOperands() : MachineFunctionPass(ID) {
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initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
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@ -686,14 +690,75 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI,
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}
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}
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const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
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unsigned Op = MI.getOpcode();
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switch (Op) {
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case AMDGPU::V_MAX_F32_e64:
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case AMDGPU::V_MAX_F16_e64: {
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if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm())
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return nullptr;
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// Make sure sources are identical.
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const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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if (!Src0->isReg() || Src0->getSubReg() != Src1->getSubReg() ||
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Src0->getSubReg() != AMDGPU::NoSubRegister)
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return nullptr;
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// Can't fold up if we have modifiers.
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if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
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TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
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TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
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return nullptr;
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return Src0;
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}
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default:
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return nullptr;
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}
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}
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// We obviously have multiple uses in a clamp since the register is used twice
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// in the same instruction.
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static bool hasOneNonDBGUseInst(const MachineRegisterInfo &MRI, unsigned Reg) {
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int Count = 0;
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for (auto I = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
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I != E; ++I) {
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if (++Count > 1)
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return false;
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}
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return true;
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}
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// FIXME: Does this need to check IEEE bit on function?
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bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) {
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const MachineOperand *ClampSrc = isClamp(MI);
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if (!ClampSrc || !hasOneNonDBGUseInst(*MRI, ClampSrc->getReg()))
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return false;
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MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
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if (!TII->hasFPClamp(*Def))
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return false;
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MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
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if (!DefClamp)
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return false;
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DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def << '\n');
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// Clamp is applied after omod, so it is OK if omod is set.
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DefClamp->setImm(1);
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MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
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MI.eraseFromParent();
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return true;
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}
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bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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MRI = &MF.getRegInfo();
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TII = ST.getInstrInfo();
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ST = &MF.getSubtarget<SISubtarget>();
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TII = ST->getInstrInfo();
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TRI = &TII->getRegisterInfo();
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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@ -705,8 +770,11 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (!isSafeToFold(MI))
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if (!isSafeToFold(MI)) {
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// TODO: Try omod also.
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tryFoldClamp(MI);
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continue;
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}
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MachineOperand &OpToFold = MI.getOperand(1);
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bool FoldingImm = OpToFold.isImm() || OpToFold.isFI();
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@ -78,6 +78,10 @@ class InstSI <dag outs, dag ins, string asm = "",
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// is unable to infer the encoding from the operands.
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field bit VOPAsmPrefer32Bit = 0;
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// This bit indicates that this has a floating point result type, so
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// the clamp modifier has floating point semantics.
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field bit FPClamp = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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@ -120,6 +124,7 @@ class InstSI <dag outs, dag ins, string asm = "",
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let TSFlags{39} = ScalarStore;
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let TSFlags{40} = FixedSize;
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let TSFlags{41} = VOPAsmPrefer32Bit;
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let TSFlags{42} = FPClamp;
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let SchedRW = [Write32Bit];
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@ -474,6 +474,14 @@ public:
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return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
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}
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static bool hasFPClamp(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::HasFPClamp;
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}
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bool hasFPClamp(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::HasFPClamp;
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}
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bool isVGPRCopy(const MachineInstr &MI) const {
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assert(MI.isCopy());
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unsigned Dest = MI.getOperand(0).getReg();
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@ -1086,6 +1086,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field bit HasOMod = HasModifiers;
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field bit HasClamp = HasModifiers;
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field bit HasSDWAClamp = HasSrc0;
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field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
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field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
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@ -100,6 +100,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP3On
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let VOP3 = 1;
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let VALU = 1;
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let FPClamp = P.HasFPClamp;
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let Uses = [EXEC];
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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@ -0,0 +1,190 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}v_clamp_add_src_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN-NOT: [[A]]
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; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}}
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define amdgpu_kernel void @v_clamp_add_src_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_multi_use_src_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}}
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; GCN: v_max_f32_e64 v{{[0-9]+}}, [[ADD]], [[ADD]] clamp{{$}}
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define amdgpu_kernel void @v_clamp_multi_use_src_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* %out.gep
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store volatile float %add, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_dbg_use_src_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN-NOT: [[A]]
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; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}}
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define amdgpu_kernel void @v_clamp_dbg_use_src_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_add_neg_src_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_floor_f32_e32 [[FLOOR:v[0-9]+]], [[A]]
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; GCN: v_max_f32_e64 v{{[0-9]+}}, -[[FLOOR]], -[[FLOOR]] clamp{{$}}
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define amdgpu_kernel void @v_clamp_add_neg_src_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%floor = call float @llvm.floor.f32(float %a)
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%neg.floor = fsub float -0.0, %floor
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%max = call float @llvm.maxnum.f32(float %neg.floor, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_non_clamp_max_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}}
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; GCN: v_max_f32_e32 v{{[0-9]+}}, 0, [[ADD]]{{$}}
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define amdgpu_kernel void @v_non_clamp_max_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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store float %max, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_add_src_f32_denormals:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], [[A]], 1.0 clamp{{$}}
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define amdgpu_kernel void @v_clamp_add_src_f32_denormals(float addrspace(1)* %out, float addrspace(1)* %aptr) #2 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_add_src_f16_denorm:
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; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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; VI: v_add_f16_e64 [[ADD:v[0-9]+]], [[A]], 1.0 clamp{{$}}
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; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]]
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; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}}
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; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[ADD]]
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define amdgpu_kernel void @v_clamp_add_src_f16_denorm(half addrspace(1)* %out, half addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr half, half addrspace(1)* %out, i32 %tid
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%a = load half, half addrspace(1)* %gep0
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%add = fadd half %a, 1.0
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%max = call half @llvm.maxnum.f16(half %add, half 0.0)
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%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
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store half %clamp, half addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_add_src_f16_no_denormals:
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; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
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; VI-NOT: [[A]]
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; VI: v_add_f16_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}}
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; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]]
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; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}}
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; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[ADD]]
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define amdgpu_kernel void @v_clamp_add_src_f16_no_denormals(half addrspace(1)* %out, half addrspace(1)* %aptr) #3 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr half, half addrspace(1)* %out, i32 %tid
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%a = load half, half addrspace(1)* %gep0
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%add = fadd half %a, 1.0
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%max = call half @llvm.maxnum.f16(half %add, half 0.0)
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%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
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store half %clamp, half addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_clamp_add_src_v2f32:
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; GCN: {{buffer|flat}}_load_dwordx2 v{{\[}}[[A:[0-9]+]]:[[B:[0-9]+]]{{\]}}
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; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[A]], 1.0 clamp{{$}}
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; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[B]], 1.0 clamp{{$}}
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define amdgpu_kernel void @v_clamp_add_src_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %out, i32 %tid
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%a = load <2 x float>, <2 x float> addrspace(1)* %gep0
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%add = fadd <2 x float> %a, <float 1.0, float 1.0>
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%max = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %add, <2 x float> zeroinitializer)
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%clamp = call <2 x float> @llvm.minnum.v2f32(<2 x float> %max, <2 x float> <float 1.0, float 1.0>)
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store <2 x float> %clamp, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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declare float @llvm.minnum.f32(float, float) #1
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declare float @llvm.maxnum.f32(float, float) #1
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declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
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declare double @llvm.fabs.f64(double) #1
|
||||
declare double @llvm.minnum.f64(double, double) #1
|
||||
declare double @llvm.maxnum.f64(double, double) #1
|
||||
declare half @llvm.fabs.f16(half) #1
|
||||
declare half @llvm.minnum.f16(half, half) #1
|
||||
declare half @llvm.maxnum.f16(half, half) #1
|
||||
declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1
|
||||
declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1
|
||||
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { nounwind "target-features"="+fp32-denormals" }
|
||||
attributes #3 = { nounwind "target-features"="-fp64-fp16-denormals" }
|
||||
|
||||
!llvm.dbg.cu = !{!0}
|
||||
!llvm.module.flags = !{!2, !3}
|
||||
|
||||
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug)
|
||||
!1 = !DIFile(filename: "/tmp/foo.cl", directory: "/dev/null")
|
||||
!2 = !{i32 2, !"Dwarf Version", i32 4}
|
||||
!3 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!4 = !DILocalVariable(name: "add", arg: 1, scope: !5, file: !1, line: 1)
|
||||
!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
|
||||
!6 = !DISubroutineType(types: !7)
|
||||
!7 = !{null, !8}
|
||||
!8 = !DIBasicType(name: "float", size: 32, align: 32)
|
||||
!9 = !DIExpression()
|
||||
!10 = !DILocation(line: 1, column: 42, scope: !5)
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
|
||||
--- |
|
||||
define amdgpu_kernel void @v_max_self_clamp_not_set_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) {
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @v_clamp_omod_already_set_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) {
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
# GCN-LABEL: name: v_max_self_clamp_not_set_f32
|
||||
# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
|
||||
# GCN-NEXT: %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
|
||||
|
||||
name: v_max_self_clamp_not_set_f32
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_64_xexec }
|
||||
- { id: 6, class: sreg_32 }
|
||||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_64 }
|
||||
- { id: 10, class: sreg_32_xm0 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sgpr_64 }
|
||||
- { id: 13, class: sgpr_128 }
|
||||
- { id: 14, class: sreg_32_xm0 }
|
||||
- { id: 15, class: sreg_64 }
|
||||
- { id: 16, class: sgpr_128 }
|
||||
- { id: 17, class: vgpr_32 }
|
||||
- { id: 18, class: vreg_64 }
|
||||
- { id: 19, class: vgpr_32 }
|
||||
- { id: 20, class: vgpr_32 }
|
||||
- { id: 21, class: vgpr_32 }
|
||||
- { id: 22, class: vgpr_32 }
|
||||
- { id: 23, class: vreg_64 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vreg_64 }
|
||||
- { id: 26, class: vreg_64 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%3' }
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%3 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
|
||||
%25 = REG_SEQUENCE %3, 1, %24, 2
|
||||
%10 = S_MOV_B32 61440
|
||||
%11 = S_MOV_B32 0
|
||||
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
||||
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
||||
%14 = S_MOV_B32 2
|
||||
%26 = V_LSHL_B64 killed %25, 2, implicit %exec
|
||||
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
||||
%18 = COPY %26
|
||||
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
|
||||
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
|
||||
%21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
|
||||
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
---
|
||||
# GCN-LABEL: name: v_clamp_omod_already_set_f32
|
||||
# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
|
||||
# GCN: %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
|
||||
name: v_clamp_omod_already_set_f32
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sgpr_64 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: sreg_64_xexec }
|
||||
- { id: 5, class: sreg_64_xexec }
|
||||
- { id: 6, class: sreg_32 }
|
||||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_64 }
|
||||
- { id: 10, class: sreg_32_xm0 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sgpr_64 }
|
||||
- { id: 13, class: sgpr_128 }
|
||||
- { id: 14, class: sreg_32_xm0 }
|
||||
- { id: 15, class: sreg_64 }
|
||||
- { id: 16, class: sgpr_128 }
|
||||
- { id: 17, class: vgpr_32 }
|
||||
- { id: 18, class: vreg_64 }
|
||||
- { id: 19, class: vgpr_32 }
|
||||
- { id: 20, class: vgpr_32 }
|
||||
- { id: 21, class: vgpr_32 }
|
||||
- { id: 22, class: vgpr_32 }
|
||||
- { id: 23, class: vreg_64 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: vreg_64 }
|
||||
- { id: 26, class: vreg_64 }
|
||||
liveins:
|
||||
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
||||
- { reg: '%vgpr0', virtual-reg: '%3' }
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
liveins: %sgpr0_sgpr1, %vgpr0
|
||||
|
||||
%3 = COPY %vgpr0
|
||||
%0 = COPY %sgpr0_sgpr1
|
||||
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
|
||||
%24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
|
||||
%25 = REG_SEQUENCE %3, 1, %24, 2
|
||||
%10 = S_MOV_B32 61440
|
||||
%11 = S_MOV_B32 0
|
||||
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
||||
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
||||
%14 = S_MOV_B32 2
|
||||
%26 = V_LSHL_B64 killed %25, 2, implicit %exec
|
||||
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
||||
%18 = COPY %26
|
||||
%17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
|
||||
%20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
|
||||
%21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
|
||||
BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -87,9 +87,8 @@ define amdgpu_kernel void @v_clamp_multi_use_max_f32(float addrspace(1)* %out, f
|
|||
; GCN: {{buffer|flat}}_load_ushort [[A:v[0-9]+]]
|
||||
; VI: v_max_f16_e64 v{{[0-9]+}}, [[A]], [[A]] clamp{{$}}
|
||||
|
||||
; SI: v_cvt_f32_f16_e32 [[CVT:v[0-9]+]], [[A]]
|
||||
; SI: v_max_f32_e64 v{{[0-9]+}}, [[CVT]], [[CVT]] clamp{{$}}
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], [[A]] clamp{{$}}
|
||||
; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[CVT]]
|
||||
define amdgpu_kernel void @v_clamp_f16(half addrspace(1)* %out, half addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
|
||||
|
|
@ -107,9 +106,8 @@ define amdgpu_kernel void @v_clamp_f16(half addrspace(1)* %out, half addrspace(1
|
|||
; VI: v_max_f16_e64 v{{[0-9]+}}, -[[A]], -[[A]] clamp{{$}}
|
||||
|
||||
; FIXME: Better to fold neg into max
|
||||
; SI: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -[[A]]
|
||||
; SI: v_max_f32_e64 v{{[0-9]+}}, [[CVT]], [[CVT]] clamp{{$}}
|
||||
; SI: v_cvt_f16_f32
|
||||
; SI: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -[[A]] clamp{{$}}
|
||||
; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[CVT]]
|
||||
define amdgpu_kernel void @v_clamp_neg_f16(half addrspace(1)* %out, half addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
|
||||
|
|
@ -129,9 +127,8 @@ define amdgpu_kernel void @v_clamp_neg_f16(half addrspace(1)* %out, half addrspa
|
|||
|
||||
; FIXME: Better to fold neg/abs into max
|
||||
|
||||
; SI: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -|[[A]]|
|
||||
; SI: v_max_f32_e64 v{{[0-9]+}}, [[CVT]], [[CVT]] clamp{{$}}
|
||||
; SI: v_cvt_f16_f32_e32
|
||||
; SI: v_cvt_f32_f16_e64 [[CVT:v[0-9]+]], -|[[A]]| clamp{{$}}
|
||||
; SI: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[CVT]]
|
||||
define amdgpu_kernel void @v_clamp_negabs_f16(half addrspace(1)* %out, half addrspace(1)* %aptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep0 = getelementptr half, half addrspace(1)* %aptr, i32 %tid
|
||||
|
|
|
|||
Loading…
Reference in New Issue