forked from OSchip/llvm-project
When promoting the result of fp_to_uint/fp_to_sint,
inform the optimizers that the result must be zero/ sign extended from the smaller type. For example, if a fp to unsigned i16 is promoted to fp to i32, then we are allowed to assume that the extra 16 bits are zero (because the result of fp to i16 is undefined if the result does not fit in an i16). This is quite aggressive, but should help the optimizers produce better code. This requires correcting a test which thought that fp_to_uint is some kind of truncation, which it is not: in the testcase (which does fp to i1), either the fp value converts to 0 or 1 or the result is undefined, which is quite different to truncation. llvm-svn: 58991
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@ -267,7 +267,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
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// matter in theory which one we pick, but this tends to give better code?
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unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
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SDValue(N, 0));
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SDValue(N, 0));
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assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
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return Result;
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}
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@ -350,22 +350,27 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
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unsigned NewOpc = N->getOpcode();
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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unsigned NewOpc = N->getOpcode();
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// If we're promoting a UINT to a larger size, check to see if the new node
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// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
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// we can use that instead. This allows us to generate better code for
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// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
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// legal, such as PowerPC.
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if (N->getOpcode() == ISD::FP_TO_UINT) {
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if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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(TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
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TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
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NewOpc = ISD::FP_TO_SINT;
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}
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if (N->getOpcode() == ISD::FP_TO_UINT &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
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NewOpc = ISD::FP_TO_SINT;
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return DAG.getNode(NewOpc, NVT, N->getOperand(0));
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SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
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// Assert that the converted value fits in the original type. If it doesn't
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// (eg: because the value being converted is too big), then the result of the
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// original operation was undefined anyway, so the assert is still correct.
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return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
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ISD::AssertZext : ISD::AssertSext,
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NVT, Res, DAG.getValueType(N->getValueType(0)));
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
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@ -2,7 +2,7 @@
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; sure only the LSBit survives. Test that this is the case both for a returned
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; value and as the operand of a branch.
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; RUN: llvm-as < %s | llc -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \
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; RUN: count 6
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; RUN: count 5
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define i1 @test1(i32 %X) zeroext {
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%Y = trunc i32 %X to i1
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@ -40,15 +40,6 @@ cond_false:
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ret i32 42
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}
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define i32 @test5(float %f) {
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%tmp = fptoui float %f to i1
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br i1 %tmp, label %cond_true, label %cond_false
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cond_true:
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ret i32 21
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cond_false:
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ret i32 42
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}
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define i32 @test6(double %d) {
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%tmp = fptosi double %d to i1
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br i1 %tmp, label %cond_true, label %cond_false
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