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[X86] Merge more instregex single matches to reduce InstrRW compile time. 

llvm-svn: 331143
This commit is contained in:
Simon Pilgrim 2018-04-29 15:33:15 +00:00
parent 684a719270
commit d5ada498db
6 changed files with 195 additions and 393 deletions
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34
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -450,9 +450,8 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Agner's data def: InstRW<[BWWriteResGroup9], (instrs LAHF, SAHF)>; // TODO: This doesnt match Agner's data
"NOOP", def: InstRW<[BWWriteResGroup9], (instregex "NOOP",
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SMSW16m", "SMSW16m",
@ -884,7 +883,7 @@ def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
let NumMicroOps = 5; let NumMicroOps = 5;
let ResourceCycles = [1,4]; let ResourceCycles = [1,4];
} }
def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>; def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> { def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 5; let Latency = 5;
@ -1197,24 +1196,15 @@ def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
let NumMicroOps = 3; let NumMicroOps = 3;
let ResourceCycles = [1,1,1]; let ResourceCycles = [1,1,1];
} }
def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm", def: InstRW<[BWWriteResGroup81], (instregex "(V?)PSLLDrm",
"PSLLQrm", "(V?)PSLLQrm",
"PSLLWrm", "(V?)PSLLWrm",
"PSRADrm", "(V?)PSRADrm",
"PSRAWrm", "(V?)PSRAWrm",
"PSRLDrm", "(V?)PSRLDrm",
"PSRLQrm", "(V?)PSRLQrm",
"PSRLWrm", "(V?)PSRLWrm",
"PTESTrm", "(V?)PTESTrm")>;
"VPSLLDrm",
"VPSLLQrm",
"VPSLLWrm",
"VPSRADrm",
"VPSRAWrm",
"VPSRLDrm",
"VPSRLQrm",
"VPSRLWrm",
"VPTESTrm")>;
def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> { def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
let Latency = 7; let Latency = 7;

4
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -450,7 +450,7 @@ def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
def HWWriteINTO : SchedWriteRes<[]> { def HWWriteINTO : SchedWriteRes<[]> {
let NumMicroOps = 4; let NumMicroOps = 4;
} }
def : InstRW<[HWWriteINTO], (instregex "INTO")>; def : InstRW<[HWWriteINTO], (instrs INTO)>;
//-- String instructions --// //-- String instructions --//
@ -1941,7 +1941,7 @@ def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
let NumMicroOps = 5; let NumMicroOps = 5;
let ResourceCycles = [1,4]; let ResourceCycles = [1,4];
} }
def: InstRW<[HWWriteResGroup99], (instregex "PAUSE")>; def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 5; let Latency = 5;

5
llvm/lib/Target/X86/X86SchedSandyBridge.td
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@ -375,6 +375,7 @@ def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
def: InstRW<[SBWriteResGroup4], (instrs LAHF, SAHF)>;
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8", def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr", "BT(16|32|64)rr",
"BTC(16|32|64)ri8", "BTC(16|32|64)ri8",
@ -383,8 +384,6 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)rr", "BTR(16|32|64)rr",
"BTS(16|32|64)ri8", "BTS(16|32|64)ri8",
"BTS(16|32|64)rr", "BTS(16|32|64)rr",
"LAHF",
"SAHF",
"VMOVDQA(Y?)rr", "VMOVDQA(Y?)rr",
"VMOVDQU(Y?)rr")>; "VMOVDQU(Y?)rr")>;
@ -712,7 +711,7 @@ def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1,3]; let ResourceCycles = [1,3];
} }
def: InstRW<[SBWriteResGroup29_2], (instregex "PAUSE")>; def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> { def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 4; let Latency = 4;

5
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -532,11 +532,10 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>; def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKLWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
def: InstRW<[SKLWriteResGroup10], (instregex "CLC", def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
"CMC", "CMC",
"LAHF", // TODO: This doesn't match Agner's data
"NOOP", "NOOP",
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SMSW16m", "SMSW16m",
@ -978,7 +977,7 @@ def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let NumMicroOps = 4; let NumMicroOps = 4;
let ResourceCycles = [1,3]; let ResourceCycles = [1,3];
} }
def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>; def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> { def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
let Latency = 4; let Latency = 4;

530
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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File diff suppressed because it is too large Load Diff

10
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -361,14 +361,14 @@ def ZnWritePushA : SchedWriteRes<[ZnAGU]> {
def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>; def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>;
//LAHF //LAHF
def : InstRW<[WriteMicrocoded], (instregex "LAHF")>; def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
// SAHF. // SAHF.
def ZnWriteSAHF : SchedWriteRes<[ZnALU]> { def ZnWriteSAHF : SchedWriteRes<[ZnALU]> {
let Latency = 2; let Latency = 2;
let NumMicroOps = 2; let NumMicroOps = 2;
} }
def : InstRW<[ZnWriteSAHF], (instregex "SAHF")>; def : InstRW<[ZnWriteSAHF], (instrs SAHF)>;
// BSWAP. // BSWAP.
def ZnWriteBSwap : SchedWriteRes<[ZnALU]> { def ZnWriteBSwap : SchedWriteRes<[ZnALU]> {
@ -513,7 +513,7 @@ def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>;
def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>; def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
// INTO // INTO
def : InstRW<[WriteMicrocoded], (instregex "INTO")>; def : InstRW<[WriteMicrocoded], (instrs INTO)>;
// LOOP. // LOOP.
def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>; def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>;
@ -634,7 +634,7 @@ def ZnWriteLEAVE : SchedWriteRes<[ZnALU, ZnAGU]> {
def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>; def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>;
// PAUSE. // PAUSE.
def : InstRW<[WriteMicrocoded], (instregex "PAUSE")>; def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
// RDTSC. // RDTSC.
def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>; def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
@ -1308,7 +1308,7 @@ def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>;
// CVTPI2PD. // CVTPI2PD.
// x,mm. // x,mm.
def : InstRW<[ZnWriteCVTPS2PDr], (instregex "MMX_CVT(T?)PI2PDirr")>; def : InstRW<[ZnWriteCVTPS2PDr], (instregex "MMX_CVTPI2PDirr")>;
// CVT(T)PD2PI. // CVT(T)PD2PI.
// mm,x. // mm,x.