forked from OSchip/llvm-project
Revert "[AArch64] added FP16 vcvth intrinsic support"
This reverts commit r333410 due to bot failures. llvm-svn: 333427
This commit is contained in:
Amara Emerson
parent
d3ce899ddf
commit
d5a9e7bbc9
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@ -7928,26 +7928,6 @@ class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
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multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
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let Predicates = [HasNEON, HasFullFP16] in {
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def HSr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
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FPR16, FPR32, vecshiftR16, asm, []> {
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let Inst{19-16} = imm{3-0};
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let Inst{23-22} = 0b11;
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}
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def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
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FPR32, FPR16, vecshiftR32, asm, []> {
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let Inst{19-16} = imm{3-0};
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}
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def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
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FPR16, FPR64, vecshiftR32, asm, []> {
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let Inst{21-16} = imm{5-0};
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let Inst{23-22} = 0b11;
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}
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def DHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
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FPR64, FPR16, vecshiftR64, asm, []> {
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let Inst{21-16} = imm{5-0};
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let Inst{23-22} = 0b11;
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let Inst{31} = 1;
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}
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def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
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FPR16, FPR16, vecshiftR16, asm, []> {
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let Inst{19-16} = imm{3-0};
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@ -7957,6 +7937,7 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
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FPR32, FPR32, vecshiftR32, asm, []> {
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let Inst{20-16} = imm{4-0};
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}
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def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
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FPR64, FPR64, vecshiftR64, asm, []> {
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let Inst{21-16} = imm{5-0};
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@ -4955,29 +4955,17 @@ def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
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def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
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vecshiftR64:$imm)),
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(FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
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(FCVTZSHDr (i64 FPR64:$Rn), vecshiftR32:$imm)>;
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def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu FPR16:$Rn, vecshiftR32:$imm)),
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(FCVTZUSHr FPR16:$Rn, vecshiftR32:$imm)>;
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def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs FPR16:$Rn, vecshiftR32:$imm)),
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(FCVTZSSHr FPR16:$Rn, vecshiftR32:$imm)>;
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def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),
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(FCVTZSDHr (f16 FPR16:$Rn), vecshiftR64:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
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(UCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
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def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
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(SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
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def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
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(UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
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def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
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(SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
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def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
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(UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
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def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
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vecshiftR64:$imm)),
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(SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
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(SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR16:$imm)),
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(SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
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def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
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(SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
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def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
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vecshiftR64:$imm)),
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(UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
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@ -126,222 +126,3 @@ entry:
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%vrsqrtsh_f16 = tail call half @llvm.aarch64.neon.frsqrts.f16(half %a, half %b)
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ret half %vrsqrtsh_f16
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}
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declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32, i32) #1
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declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64, i32) #1
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declare i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half, i32) #1
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declare i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half, i32) #1
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declare half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32, i32) #1
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declare i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half, i32) #1
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define dso_local half @test_vcvth_n_f16_s16_1(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s16_1:
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; CHECK: sxth w[[wReg:[0-9]+]], w0
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; CHECK-NEXT: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: scvtf h0, s0, #1
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; CHECK-NEXT: ret
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entry:
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%sext = sext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_s16_16(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s16_16:
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; CHECK: sxth w[[wReg:[0-9]+]], w0
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; CHECK-NEXT: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: scvtf h0, s0, #16
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; CHECK-NEXT: ret
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entry:
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%sext = sext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 16)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_s32_1(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s32_1:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: scvtf h0, s0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 1)
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ret half %vcvth_n_f16_s32
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}
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define dso_local half @test_vcvth_n_f16_s32_16(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s32_16:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: scvtf h0, s0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 16)
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ret half %vcvth_n_f16_s32
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}
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define dso_local half @test_vcvth_n_f16_s64_1(i64 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s64_1:
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; CHECK: fmov d0, x0
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; CHECK-NEXT: fcvtzs h0, d0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 1)
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ret half %vcvth_n_f16_s64
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}
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define dso_local half @test_vcvth_n_f16_s64_16(i64 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s64_16:
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; CHECK: fmov d0, x0
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; CHECK-NEXT: fcvtzs h0, d0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
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ret half %vcvth_n_f16_s64
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}
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define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s16_f16_1:
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; CHECK: fcvtzs s0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i16 @test_vcvth_n_s16_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_s16_f16_16:
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; CHECK: fcvtzs s0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i32 @test_vcvth_n_s32_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s32_f16_1:
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; CHECK: fcvtzs s0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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ret i32 %vcvth_n_s32_f16
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}
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define dso_local i32 @test_vcvth_n_s32_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_s32_f16_16:
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; CHECK: fcvtzs s0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)
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ret i32 %vcvth_n_s32_f16
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}
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define dso_local i64 @test_vcvth_n_s64_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s64_f16_1:
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; CHECK: fcvtzs d0, h0, #1
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 1)
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ret i64 %vcvth_n_s64_f16
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}
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define dso_local i64 @test_vcvth_n_s64_f16_32(half %a) {
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; CHECK-LABEL: test_vcvth_n_s64_f16_32:
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; CHECK: fcvtzs d0, h0, #32
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 32)
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ret i64 %vcvth_n_s64_f16
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}
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define dso_local half @test_vcvth_n_f16_u16_1(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u16_1:
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; CHECK: and w[[wReg:[0-9]+]], w0, #0xffff
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; CHECK-NEXT: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: ucvtf h0, s0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = zext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 1)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_u16_16(i16 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u16_16:
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; CHECK: and w[[wReg:[0-9]+]], w0, #0xffff
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; CHECK-NEXT: fmov s0, w[[wReg:[0-9]+]]
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; CHECK-NEXT: ucvtf h0, s0, #16
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; CHECK-NEXT: ret
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entry:
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%0 = zext i16 %a to i32
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%fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 16)
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ret half %fcvth_n
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}
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define dso_local half @test_vcvth_n_f16_u32_1(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u32_1:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: ucvtf h0, s0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 1)
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ret half %vcvth_n_f16_u32
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}
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define dso_local half @test_vcvth_n_f16_u32_16(i32 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_u32_16:
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; CHECK: fmov s0, w0
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; CHECK-NEXT: ucvtf h0, s0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 16)
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ret half %vcvth_n_f16_u32
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}
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define dso_local i16 @test_vcvth_n_u16_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_u16_f16_1:
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; CHECK: fcvtzu s0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i16 @test_vcvth_n_u16_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_u16_f16_16:
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; CHECK: fcvtzu s0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
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%0 = trunc i32 %fcvth_n to i16
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ret i16 %0
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}
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define dso_local i32 @test_vcvth_n_u32_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_u32_f16_1:
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; CHECK: fcvtzu s0, h0, #1
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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ret i32 %vcvth_n_u32_f16
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}
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define dso_local i32 @test_vcvth_n_u32_f16_16(half %a) {
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; CHECK-LABEL: test_vcvth_n_u32_f16_16:
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; CHECK: fcvtzu s0, h0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
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ret i32 %vcvth_n_u32_f16
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}
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