forked from OSchip/llvm-project
parent
780507c183
commit
d56a27e242
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@ -1,96 +1,107 @@
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; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s -check-prefix=32
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64
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; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; rdar://7573216
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; rdar://7573216
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; PR6146
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; PR6146
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define i32 @t1(i32 %x) nounwind readnone ssp {
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define i32 @t1(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; 32-LABEL: t1:
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; CHECK: # BB#0:
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; 32: cmpl $1
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; CHECK-NEXT: cmpl $1
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; 32: sbbl
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; CHECK-NEXT: sbbl %eax, %eax
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; CHECK-NEXT: ret
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; 64-LABEL: t1:
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;
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; 64: cmpl $1
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%t0 = icmp eq i32 %x, 0
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; 64: sbbl
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%if = select i1 %t0, i32 -1, i32 0
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%0 = icmp eq i32 %x, 0
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ret i32 %if
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%iftmp.0.0 = select i1 %0, i32 -1, i32 0
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ret i32 %iftmp.0.0
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}
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}
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define i32 @t2(i32 %x) nounwind readnone ssp {
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define i32 @t2(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; 32-LABEL: t2:
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; CHECK: # BB#0:
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; 32: cmpl $1
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; CHECK-NEXT: cmpl $1
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; 32: sbbl
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; CHECK-NEXT: sbbl %eax, %eax
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; CHECK-NEXT: ret
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; 64-LABEL: t2:
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;
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; 64: cmpl $1
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%t0 = icmp eq i32 %x, 0
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; 64: sbbl
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%if = sext i1 %t0 to i32
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%0 = icmp eq i32 %x, 0
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ret i32 %if
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%iftmp.0.0 = sext i1 %0 to i32
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ret i32 %iftmp.0.0
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}
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}
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%struct.zbookmark = type { i64, i64 }
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%struct.zstream = type { }
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define i32 @t3() nounwind readonly {
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define i32 @t3() nounwind readonly {
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; X32-LABEL: t3:
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; X32: # BB#0: # %entry
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; X32-NEXT: cmpl $1, %eax
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: cmpl %eax, %eax
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t3:
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; X64: # BB#0: # %entry
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; X64-NEXT: cmpl $1, %eax
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; X64-NEXT: sbbq %rax, %rax
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; X64-NEXT: cmpq %rax, %rax
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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;
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entry:
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entry:
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; 32-LABEL: t3:
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%not.tobool = icmp eq i32 undef, 0
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; 32: cmpl $1
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%cond = sext i1 %not.tobool to i32
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; 32: sbbl
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%conv = sext i1 %not.tobool to i64
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; 32: cmpl
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%add13 = add i64 0, %conv
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; 32: xorl
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%cmp = icmp ult i64 undef, %add13
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; 64-LABEL: t3:
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; 64: cmpl $1
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; 64: sbbq
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; 64: cmpq
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; 64: xorl
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%not.tobool = icmp eq i32 undef, 0 ; <i1> [#uses=2]
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%cond = sext i1 %not.tobool to i32 ; <i32> [#uses=1]
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%conv = sext i1 %not.tobool to i64 ; <i64> [#uses=1]
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%add13 = add i64 0, %conv ; <i64> [#uses=1]
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%cmp = icmp ult i64 undef, %add13 ; <i1> [#uses=1]
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br i1 %cmp, label %if.then, label %if.end
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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if.then:
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br label %if.end
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br label %if.end
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if.end: ; preds = %if.then, %entry
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if.end:
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%xor27 = xor i32 undef, %cond ; <i32> [#uses=0]
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%xor27 = xor i32 undef, %cond
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ret i32 0
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ret i32 0
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}
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}
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define i32 @t4(i64 %x) nounwind readnone ssp {
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define i32 @t4(i64 %x) nounwind readnone ssp {
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entry:
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; X32-LABEL: t4:
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; 32-LABEL: t4:
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; X32: # BB#0:
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; 32: movl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 32: orl
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; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
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; 32: movl
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; X32-NEXT: movl $-1, %eax
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; 32: je
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; X32-NEXT: je .LBB3_2
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; 32: xorl
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; X32-NEXT: # BB#1:
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; X32-NEXT: xorl %eax, %eax
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; 64-LABEL: t4:
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; X32-NEXT: .LBB3_2:
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; 64: cmpq $1
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; X32-NEXT: retl
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; 64: sbbl
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;
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%0 = icmp eq i64 %x, 0
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; X64-LABEL: t4:
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%1 = sext i1 %0 to i32
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; X64: # BB#0:
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ret i32 %1
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; X64-NEXT: cmpq $1, %rdi
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; X64-NEXT: sbbl %eax, %eax
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; X64-NEXT: retq
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;
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%t0 = icmp eq i64 %x, 0
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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}
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define i64 @t5(i32 %x) nounwind readnone ssp {
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define i64 @t5(i32 %x) nounwind readnone ssp {
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entry:
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; X32-LABEL: t5:
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; 32-LABEL: t5:
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; X32: # BB#0:
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; 32: cmpl $1
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; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
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; 32: sbbl
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; X32-NEXT: sbbl %eax, %eax
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; 32: movl
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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; 64-LABEL: t5:
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;
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; 64: cmpl $1
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; X64-LABEL: t5:
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; 64: sbbq
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; X64: # BB#0:
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%0 = icmp eq i32 %x, 0
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; X64-NEXT: cmpl $1, %edi
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%1 = sext i1 %0 to i64
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; X64-NEXT: sbbq %rax, %rax
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ret i64 %1
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; X64-NEXT: retq
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;
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%t0 = icmp eq i32 %x, 0
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%t1 = sext i1 %t0 to i64
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ret i64 %t1
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}
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}
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