forked from OSchip/llvm-project
[NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes
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@ -2962,14 +2962,15 @@ let Uses = [EAX], SchedRW = [WriteSystem] in
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SERIALIZE Instruction
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// SERIALIZE Instruction
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//
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//
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def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize",
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let SchedRW = [WriteSystem] in
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[(int_x86_serialize)]>, PS,
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def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize",
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Requires<[HasSERIALIZE]>;
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[(int_x86_serialize)]>, PS,
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Requires<[HasSERIALIZE]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TSXLDTRK - TSX Suspend Load Address Tracking
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// TSXLDTRK - TSX Suspend Load Address Tracking
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//
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//
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let Predicates = [HasTSXLDTRK] in {
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let Predicates = [HasTSXLDTRK], SchedRW = [WriteSystem] in {
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def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk",
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def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk",
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[(int_x86_xsusldtrk)]>, XD;
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[(int_x86_xsusldtrk)]>, XD;
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def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk",
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def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk",
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@ -2979,7 +2980,7 @@ let Predicates = [HasTSXLDTRK] in {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// UINTR Instructions
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// UINTR Instructions
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//
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//
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let Predicates = [HasUINTR, In64BitMode] in {
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let Predicates = [HasUINTR, In64BitMode], SchedRW = [WriteSystem] in {
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def UIRET : I<0x01, MRM_EC, (outs), (ins), "uiret",
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def UIRET : I<0x01, MRM_EC, (outs), (ins), "uiret",
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[]>, XS;
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[]>, XS;
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def CLUI : I<0x01, MRM_EE, (outs), (ins), "clui",
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def CLUI : I<0x01, MRM_EE, (outs), (ins), "clui",
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@ -47,15 +47,12 @@ let Uses = [EFLAGS] in
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
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} // SchedRW
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def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
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def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
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// The long form of "int $3" turns into int3 as a size optimization.
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// The long form of "int $3" turns into int3 as a size optimization.
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// FIXME: This doesn't work because InstAlias can't match immediate constants.
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// FIXME: This doesn't work because InstAlias can't match immediate constants.
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//def : InstAlias<"int\t$3", (INT3)>;
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//def : InstAlias<"int\t$3", (INT3)>;
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let SchedRW = [WriteSystem] in {
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def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
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def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
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[(int_x86_int timm:$trap)]>;
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[(int_x86_int timm:$trap)]>;
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