forked from OSchip/llvm-project
[ARM] Constant predicate tests. NFC
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David Green
parent
112b3cb6ba
commit
d5387c044d
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc void @reg(<8 x i16> %acc0, <8 x i16> %acc1, i32* nocapture %px, i16 signext %p0) {
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; CHECK-LABEL: reg:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r6, r7, lr}
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; CHECK-NEXT: push {r4, r6, r7, lr}
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, #8
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; CHECK-NEXT: movw r1, #52428
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: movw r1, #13107
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; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvt.s16 r12, q1
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvt.s16 r2, q1
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; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvt.s16 r4, q0
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; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddvt.s16 r6, q0
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; CHECK-NEXT: strd r6, r4, [r0]
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; CHECK-NEXT: strd r2, r12, [r0, #8]
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; CHECK-NEXT: add sp, #8
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; CHECK-NEXT: pop {r4, r6, r7, pc}
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entry:
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%0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107)
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%1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)
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%2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
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%3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)
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%4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)
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%5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)
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store i32 %1, i32* %px, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %px, i32 1
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store i32 %3, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %px, i32 2
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store i32 %4, i32* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %px, i32 3
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store i32 %5, i32* %arrayidx3, align 4
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ret void
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}
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define arm_aapcs_vfpcc void @const(<8 x i16> %acc0, <8 x i16> %acc1, i32* nocapture %px, i16 signext %p0) {
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; CHECK-LABEL: const:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r6, r7, lr}
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; CHECK-NEXT: push {r4, r6, r7, lr}
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; CHECK-NEXT: uxth r2, r1
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; CHECK-NEXT: mvns r1, r1
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; CHECK-NEXT: vmsr p0, r2
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; CHECK-NEXT: uxth r1, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvt.s16 r12, q1
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; CHECK-NEXT: vaddvt.s16 r2, q0
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vaddvt.s16 r4, q1
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; CHECK-NEXT: vaddvt.s16 r6, q0
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; CHECK-NEXT: stm.w r0, {r2, r6, r12}
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; CHECK-NEXT: str r4, [r0, #12]
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; CHECK-NEXT: pop {r4, r6, r7, pc}
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entry:
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%0 = zext i16 %p0 to i32
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%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %1)
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%3 = xor i16 %p0, -1
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%4 = zext i16 %3 to i32
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%5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
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%6 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %5)
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%7 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %1)
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%8 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %5)
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store i32 %2, i32* %px, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %px, i32 1
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store i32 %6, i32* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %px, i32 2
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store i32 %7, i32* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %px, i32 3
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store i32 %8, i32* %arrayidx3, align 4
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ret void
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}
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define arm_aapcs_vfpcc <4 x i32> @xorvpnot_i32(<4 x i32> %acc0, i16 signext %p0) {
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; CHECK-LABEL: xorvpnot_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvns r0, r0
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%l3 = xor i16 %p0, -1
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%l4 = zext i16 %l3 to i32
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%l5 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l4)
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%l6 = select <4 x i1> %l5, <4 x i32> %acc0, <4 x i32> zeroinitializer
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ret <4 x i32> %l6
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}
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define arm_aapcs_vfpcc <8 x i16> @xorvpnot_i16(<8 x i16> %acc0, i16 signext %p0) {
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; CHECK-LABEL: xorvpnot_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvns r0, r0
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%l3 = xor i16 %p0, -1
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%l4 = zext i16 %l3 to i32
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%l5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l4)
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%l6 = select <8 x i1> %l5, <8 x i16> %acc0, <8 x i16> zeroinitializer
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ret <8 x i16> %l6
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}
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define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8(<16 x i8> %acc0, i16 signext %p0) {
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; CHECK-LABEL: xorvpnot_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvns r0, r0
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%l3 = xor i16 %p0, -1
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%l4 = zext i16 %l3 to i32
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%l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l4)
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%l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer
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ret <16 x i8> %l6
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}
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declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
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declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)
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declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>)
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