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[Hexagon] Check validity of register class when generating bitsplit 

llvm-svn: 341137
This commit is contained in:
Krzysztof Parzyszek 2018-08-30 22:26:43 +00:00
parent d5d0a4d27f
commit d51f7b3b43
2 changed files with 44 additions and 0 deletions
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4
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
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@ -2227,6 +2227,10 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
for (unsigned S = AVs.find_first(); S; S = AVs.find_next(S)) {
// The number of leading zeros here should be the number of trailing
// non-zeros in RC.
unsigned SRC = MRI.getRegClass(S)->getID();
if (SRC != Hexagon::IntRegsRegClassID &&
SRC != Hexagon::DoubleRegsRegClassID)
continue;
if (!BT.has(S))
continue;
const BitTracker::RegisterCell &SC = BT.lookup(S);

40
llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
; Check for successful compilation.
; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31)
; This cannot be a .mir test, because the failure depends on ordering of
; virtual registers, and the .mir loader renumbers them in a way that hides
; the problem.
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; Function Attrs: nounwind
define void @f0() #0 align 2 {
b0:
br label %b1
b1: ; preds = %b3, %b0
%v0 = phi i64 [ 0, %b0 ], [ %v6, %b3 ]
br i1 undef, label %b2, label %b3
b2: ; preds = %b1
br label %b3
b3: ; preds = %b2, %b1
%v1 = phi i64 [ undef, %b2 ], [ %v0, %b1 ]
%v2 = and i64 %v1, 1
%v3 = trunc i64 %v2 to i32
%v4 = tail call i32 @llvm.hexagon.C2.mux(i32 %v3, i32 undef, i32 undef)
%v5 = trunc i32 %v4 to i8
store i8 %v5, i8* undef, align 1
%v6 = lshr i64 %v1, 1
br label %b1
}
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" }
attributes #1 = { nounwind readnone }